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@@ -237,8 +237,6 @@ ENTRY(stext)
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bl el2_setup // Drop to EL1, w20=cpu_boot_mode
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bl el2_setup // Drop to EL1, w20=cpu_boot_mode
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adrp x24, __PHYS_OFFSET
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adrp x24, __PHYS_OFFSET
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bl set_cpu_boot_mode_flag
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bl set_cpu_boot_mode_flag
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-
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- bl __vet_fdt
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bl __create_page_tables // x25=TTBR0, x26=TTBR1
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bl __create_page_tables // x25=TTBR0, x26=TTBR1
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/*
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/*
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* The following calls CPU setup code, see arch/arm64/mm/proc.S for
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* The following calls CPU setup code, see arch/arm64/mm/proc.S for
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@@ -269,24 +267,6 @@ preserve_boot_args:
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b __inval_cache_range // tail call
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b __inval_cache_range // tail call
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ENDPROC(preserve_boot_args)
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ENDPROC(preserve_boot_args)
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-/*
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- * Determine validity of the x21 FDT pointer.
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- * The dtb must be 8-byte aligned and live in the first 512M of memory.
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- */
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-__vet_fdt:
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- tst x21, #0x7
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- b.ne 1f
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- cmp x21, x24
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- b.lt 1f
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- mov x0, #(1 << 29)
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- add x0, x0, x24
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- cmp x21, x0
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- b.ge 1f
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- ret
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-1:
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- mov x21, #0
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- ret
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-ENDPROC(__vet_fdt)
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/*
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/*
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* Macro to create a table entry to the next page.
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* Macro to create a table entry to the next page.
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*
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*
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@@ -348,8 +328,7 @@ ENDPROC(__vet_fdt)
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* required to get the kernel running. The following sections are required:
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* required to get the kernel running. The following sections are required:
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* - identity mapping to enable the MMU (low address, TTBR0)
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* - identity mapping to enable the MMU (low address, TTBR0)
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* - first few MB of the kernel linear mapping to jump to once the MMU has
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* - first few MB of the kernel linear mapping to jump to once the MMU has
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- * been enabled, including the FDT blob (TTBR1)
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- * - pgd entry for fixed mappings (TTBR1)
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+ * been enabled
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*/
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*/
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__create_page_tables:
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__create_page_tables:
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adrp x25, idmap_pg_dir
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adrp x25, idmap_pg_dir
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@@ -438,22 +417,6 @@ __create_page_tables:
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mov x3, x24 // phys offset
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mov x3, x24 // phys offset
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create_block_map x0, x7, x3, x5, x6
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create_block_map x0, x7, x3, x5, x6
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- /*
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- * Map the FDT blob (maximum 2MB; must be within 512MB of
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- * PHYS_OFFSET).
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- */
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- mov x3, x21 // FDT phys address
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- and x3, x3, #~((1 << 21) - 1) // 2MB aligned
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- mov x6, #PAGE_OFFSET
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- sub x5, x3, x24 // subtract PHYS_OFFSET
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- tst x5, #~((1 << 29) - 1) // within 512MB?
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- csel x21, xzr, x21, ne // zero the FDT pointer
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- b.ne 1f
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- add x5, x5, x6 // __va(FDT blob)
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- add x6, x5, #1 << 21 // 2MB for the FDT blob
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- sub x6, x6, #1 // inclusive range
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- create_block_map x0, x7, x3, x5, x6
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-1:
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/*
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/*
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* Since the page tables have been populated with non-cacheable
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* Since the page tables have been populated with non-cacheable
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* accesses (MMU disabled), invalidate the idmap and swapper page
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* accesses (MMU disabled), invalidate the idmap and swapper page
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