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@@ -510,7 +510,7 @@ static int ath10k_download_fw(struct ath10k *ar, enum ath10k_firmware_mode mode)
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data_len = ar->firmware_len;
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mode_name = "normal";
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ret = ath10k_swap_code_seg_configure(ar,
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- ATH10K_SWAP_CODE_SEG_BIN_TYPE_FW);
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+ ATH10K_SWAP_CODE_SEG_BIN_TYPE_FW);
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if (ret) {
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ath10k_err(ar, "failed to configure fw code swap: %d\n",
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ret);
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@@ -1263,10 +1263,10 @@ int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode)
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goto err;
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/* Some of of qca988x solutions are having global reset issue
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- * during target initialization. Bypassing PLL setting before
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- * downloading firmware and letting the SoC run on REF_CLK is
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- * fixing the problem. Corresponding firmware change is also needed
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- * to set the clock source once the target is initialized.
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+ * during target initialization. Bypassing PLL setting before
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+ * downloading firmware and letting the SoC run on REF_CLK is
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+ * fixing the problem. Corresponding firmware change is also needed
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+ * to set the clock source once the target is initialized.
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*/
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if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT,
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ar->fw_features)) {
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