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@@ -1502,14 +1502,18 @@ static void arizona_apply_fll(struct arizona *arizona, unsigned int base,
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cfg->refdiv << ARIZONA_FLL1_CLK_REF_DIV_SHIFT |
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source << ARIZONA_FLL1_CLK_REF_SRC_SHIFT);
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- if (sync)
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- regmap_update_bits_async(arizona->regmap, base + 0x7,
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- ARIZONA_FLL1_GAIN_MASK,
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- cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
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- else
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- regmap_update_bits_async(arizona->regmap, base + 0x9,
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- ARIZONA_FLL1_GAIN_MASK,
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- cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
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+ if (sync) {
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+ regmap_update_bits(arizona->regmap, base + 0x7,
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+ ARIZONA_FLL1_GAIN_MASK,
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+ cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
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+ } else {
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+ regmap_update_bits(arizona->regmap, base + 0x5,
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+ ARIZONA_FLL1_OUTDIV_MASK,
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+ cfg->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
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+ regmap_update_bits(arizona->regmap, base + 0x9,
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+ ARIZONA_FLL1_GAIN_MASK,
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+ cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
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+ }
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regmap_update_bits_async(arizona->regmap, base + 2,
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ARIZONA_FLL1_CTRL_UPD | ARIZONA_FLL1_N_MASK,
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@@ -1546,10 +1550,6 @@ static void arizona_enable_fll(struct arizona_fll *fll,
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*/
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if (fll->ref_src >= 0 && fll->ref_freq &&
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fll->ref_src != fll->sync_src) {
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- regmap_update_bits_async(arizona->regmap, fll->base + 5,
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- ARIZONA_FLL1_OUTDIV_MASK,
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- ref->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
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-
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arizona_apply_fll(arizona, fll->base, ref, fll->ref_src,
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false);
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if (fll->sync_src >= 0) {
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@@ -1558,10 +1558,6 @@ static void arizona_enable_fll(struct arizona_fll *fll,
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use_sync = true;
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}
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} else if (fll->sync_src >= 0) {
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- regmap_update_bits_async(arizona->regmap, fll->base + 5,
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- ARIZONA_FLL1_OUTDIV_MASK,
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- sync->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
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-
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arizona_apply_fll(arizona, fll->base, sync,
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fll->sync_src, false);
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