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@@ -289,6 +289,22 @@ static void at91_ddr_standby(void)
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at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
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}
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+static void sama5d3_ddr_standby(void)
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+{
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+ u32 lpr0;
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+ u32 saved_lpr0;
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+
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+ saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
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+ lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
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+ lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
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+
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+ at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
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+
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+ cpu_do_idle();
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+
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+ at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
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+}
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+
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/* We manage both DDRAM/SDRAM controllers, we need more than one value to
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* remember.
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*/
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@@ -323,7 +339,7 @@ static const struct of_device_id const ramc_ids[] __initconst = {
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{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
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{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
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{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
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- { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
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+ { .compatible = "atmel,sama5d3-ddramc", .data = sama5d3_ddr_standby },
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{ /*sentinel*/ }
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};
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