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ASoC: tlv320aic32x4: Fix MICPGA input configuration

Currently the Negative Terminal Input Routing Configuration is only set
when there is a special routing configuration. If we don't use one of
the inputs IN1 or IN2 as negative terminal input, the PGA and recording
does not work.

This patch adds a route from CM1L/CM1R to the PGA as negative input by
default. With this configuration the PGA can amplify all input signals
and line-in/mic works again.

Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
Markus Pargmann 11 ani în urmă
părinte
comite
609e6025b8
2 a modificat fișierele cu 8 adăugiri și 4 ștergeri
  1. 6 4
      sound/soc/codecs/tlv320aic32x4.c
  2. 2 0
      sound/soc/codecs/tlv320aic32x4.h

+ 6 - 4
sound/soc/codecs/tlv320aic32x4.c

@@ -618,12 +618,14 @@ static int aic32x4_probe(struct snd_soc_codec *codec)
 	snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg);
 	snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg);
 
 
 	/* Mic PGA routing */
 	/* Mic PGA routing */
-	if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) {
+	if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
 		snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_IN2R_10K);
 		snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_IN2R_10K);
-	}
-	if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) {
+	else
+		snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_CM1L_10K);
+	if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
 		snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_IN1L_10K);
 		snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_IN1L_10K);
-	}
+	else
+		snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_CM1R_10K);
 
 
 	aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 	aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
 

+ 2 - 0
sound/soc/codecs/tlv320aic32x4.h

@@ -120,7 +120,9 @@
 #define AIC32X4_MICBIAS_2075V		0x60
 #define AIC32X4_MICBIAS_2075V		0x60
 
 
 #define AIC32X4_LMICPGANIN_IN2R_10K	0x10
 #define AIC32X4_LMICPGANIN_IN2R_10K	0x10
+#define AIC32X4_LMICPGANIN_CM1L_10K	0x40
 #define AIC32X4_RMICPGANIN_IN1L_10K	0x10
 #define AIC32X4_RMICPGANIN_IN1L_10K	0x10
+#define AIC32X4_RMICPGANIN_CM1R_10K	0x40
 
 
 #define AIC32X4_LMICPGAVOL_NOGAIN	0x80
 #define AIC32X4_LMICPGAVOL_NOGAIN	0x80
 #define AIC32X4_RMICPGAVOL_NOGAIN	0x80
 #define AIC32X4_RMICPGAVOL_NOGAIN	0x80