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@@ -77,6 +77,8 @@
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#define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF 0x40
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#define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \
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MLXPLAT_CPLD_AGGR_FAN_MASK_DEF)
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+#define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04
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+#define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc0
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#define MLXPLAT_CPLD_AGGR_MASK_MSN21XX 0x04
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#define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0)
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#define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0)
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@@ -295,14 +297,29 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = {
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.mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
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};
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+static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_pwr_items_data[] = {
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+ {
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+ .label = "pwr1",
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+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
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+ .mask = BIT(0),
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+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
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+ },
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+ {
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+ .label = "pwr2",
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+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
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+ .mask = BIT(1),
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+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
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+ },
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+};
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+
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/* Platform hotplug MSN21xx system family data */
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static struct mlxreg_core_item mlxplat_mlxcpld_msn21xx_items[] = {
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{
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- .data = mlxplat_mlxcpld_default_pwr_items_data,
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+ .data = mlxplat_mlxcpld_msn21xx_pwr_items_data,
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.aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF,
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.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
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.mask = MLXPLAT_CPLD_PWR_MASK,
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- .count = ARRAY_SIZE(mlxplat_mlxcpld_pwr),
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+ .count = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_pwr_items_data),
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.inversed = 0,
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.health = false,
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},
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@@ -314,6 +331,8 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn21xx_data = {
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.counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_items),
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.cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
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.mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
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+ .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
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+ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
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};
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static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
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