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@@ -100,16 +100,17 @@ static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
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}
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/**
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- * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
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+ * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
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* @hw: pointer to the hardware structure
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* @addr: I2C bus address to read from
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* @reg: I2C device register to read from
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* @val: pointer to location to receive read value
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+ * @lock: true if to take and release semaphore
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*
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* Returns an error code on error.
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- **/
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-s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
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- u16 reg, u16 *val)
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+ */
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+static s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
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+ u16 reg, u16 *val, bool lock)
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{
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u32 swfw_mask = hw->phy.phy_semaphore_mask;
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int max_retry = 10;
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@@ -124,7 +125,7 @@ s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
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csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
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csum = ~csum;
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do {
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- if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
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+ if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
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return IXGBE_ERR_SWFW_SYNC;
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ixgbe_i2c_start(hw);
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/* Device Address and write indication */
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@@ -157,13 +158,15 @@ s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
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if (ixgbe_clock_out_i2c_bit(hw, false))
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goto fail;
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ixgbe_i2c_stop(hw);
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- hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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+ if (lock)
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+ hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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*val = (high_bits << 8) | low_bits;
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return 0;
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fail:
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ixgbe_i2c_bus_clear(hw);
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- hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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+ if (lock)
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+ hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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retry++;
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if (retry < max_retry)
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hw_dbg(hw, "I2C byte read combined error - Retry.\n");
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@@ -175,17 +178,49 @@ fail:
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}
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/**
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- * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
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+ * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
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+ * @hw: pointer to the hardware structure
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+ * @addr: I2C bus address to read from
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+ * @reg: I2C device register to read from
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+ * @val: pointer to location to receive read value
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+ *
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+ * Returns an error code on error.
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+ */
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+s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
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+ u16 reg, u16 *val)
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+{
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+ return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
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+}
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+
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+/**
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+ * ixgbe_read_i2c_combined_generic_unlocked - Unlocked I2C read combined
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+ * @hw: pointer to the hardware structure
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+ * @addr: I2C bus address to read from
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+ * @reg: I2C device register to read from
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+ * @val: pointer to location to receive read value
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+ *
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+ * Returns an error code on error.
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+ */
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+s32 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
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+ u16 reg, u16 *val)
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+{
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+ return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
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+}
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+
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+/**
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+ * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
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* @hw: pointer to the hardware structure
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* @addr: I2C bus address to write to
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* @reg: I2C device register to write to
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* @val: value to write
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+ * @lock: true if to take and release semaphore
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*
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* Returns an error code on error.
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- **/
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-s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
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- u8 addr, u16 reg, u16 val)
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+ */
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+static s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
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+ u16 reg, u16 val, bool lock)
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{
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+ u32 swfw_mask = hw->phy.phy_semaphore_mask;
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int max_retry = 1;
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int retry = 0;
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u8 reg_high;
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@@ -197,6 +232,8 @@ s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
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csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
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csum = ~csum;
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do {
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+ if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
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+ return IXGBE_ERR_SWFW_SYNC;
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ixgbe_i2c_start(hw);
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/* Device Address and write indication */
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if (ixgbe_out_i2c_byte_ack(hw, addr))
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@@ -217,10 +254,14 @@ s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
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if (ixgbe_out_i2c_byte_ack(hw, csum))
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goto fail;
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ixgbe_i2c_stop(hw);
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+ if (lock)
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+ hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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return 0;
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fail:
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ixgbe_i2c_bus_clear(hw);
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+ if (lock)
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+ hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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retry++;
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if (retry < max_retry)
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hw_dbg(hw, "I2C byte write combined error - Retry.\n");
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@@ -231,6 +272,36 @@ fail:
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return IXGBE_ERR_I2C;
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}
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+/**
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+ * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
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+ * @hw: pointer to the hardware structure
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+ * @addr: I2C bus address to write to
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+ * @reg: I2C device register to write to
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+ * @val: value to write
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+ *
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+ * Returns an error code on error.
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+ */
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+s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
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+ u8 addr, u16 reg, u16 val)
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+{
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+ return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
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+}
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+
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+/**
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+ * ixgbe_write_i2c_combined_generic_unlocked - Unlocked I2C write combined
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+ * @hw: pointer to the hardware structure
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+ * @addr: I2C bus address to write to
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+ * @reg: I2C device register to write to
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+ * @val: value to write
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+ *
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+ * Returns an error code on error.
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+ */
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+s32 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
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+ u8 addr, u16 reg, u16 val)
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+{
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+ return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
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+}
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+
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/**
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* ixgbe_identify_phy_generic - Get physical layer module
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* @hw: pointer to hardware structure
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@@ -1100,6 +1171,9 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
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return IXGBE_ERR_SFP_NOT_PRESENT;
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}
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+ /* LAN ID is needed for sfp_type determination */
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+ hw->mac.ops.set_lan_id(hw);
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+
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status = hw->phy.ops.read_i2c_eeprom(hw,
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IXGBE_SFF_IDENTIFIER,
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&identifier);
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@@ -1107,9 +1181,6 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
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if (status)
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goto err_read_i2c_eeprom;
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- /* LAN ID is needed for sfp_type determination */
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- hw->mac.ops.set_lan_id(hw);
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-
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if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
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hw->phy.type = ixgbe_phy_sfp_unsupported;
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return IXGBE_ERR_SFP_NOT_SUPPORTED;
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@@ -1660,26 +1731,28 @@ s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
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}
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/**
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- * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
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+ * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
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* @hw: pointer to hardware structure
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* @byte_offset: byte offset to read
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* @data: value read
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+ * @lock: true if to take and release semaphore
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*
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* Performs byte read operation to SFP module's EEPROM over I2C interface at
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* a specified device address.
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- **/
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-s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
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- u8 dev_addr, u8 *data)
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+ */
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+static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
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+ u8 dev_addr, u8 *data, bool lock)
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{
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s32 status;
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u32 max_retry = 10;
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u32 retry = 0;
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u32 swfw_mask = hw->phy.phy_semaphore_mask;
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bool nack = true;
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+
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*data = 0;
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do {
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- if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
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+ if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
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return IXGBE_ERR_SWFW_SYNC;
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ixgbe_i2c_start(hw);
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@@ -1721,12 +1794,16 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
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goto fail;
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ixgbe_i2c_stop(hw);
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- break;
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+ if (lock)
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+ hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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+ return 0;
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fail:
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ixgbe_i2c_bus_clear(hw);
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- hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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- msleep(100);
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+ if (lock) {
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+ hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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+ msleep(100);
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+ }
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retry++;
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if (retry < max_retry)
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hw_dbg(hw, "I2C byte read error - Retrying.\n");
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@@ -1735,29 +1812,60 @@ fail:
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} while (retry < max_retry);
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- hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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-
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return status;
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}
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/**
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- * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
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+ * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
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+ * @hw: pointer to hardware structure
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+ * @byte_offset: byte offset to read
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+ * @data: value read
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+ *
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+ * Performs byte read operation to SFP module's EEPROM over I2C interface at
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+ * a specified device address.
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+ */
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+s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
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+ u8 dev_addr, u8 *data)
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+{
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+ return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
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+ data, true);
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+}
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+
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+/**
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+ * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
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+ * @hw: pointer to hardware structure
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+ * @byte_offset: byte offset to read
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+ * @data: value read
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+ *
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+ * Performs byte read operation to SFP module's EEPROM over I2C interface at
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+ * a specified device address.
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+ */
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+s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
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+ u8 dev_addr, u8 *data)
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+{
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+ return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
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+ data, false);
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+}
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+
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+/**
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+ * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
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* @hw: pointer to hardware structure
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* @byte_offset: byte offset to write
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* @data: value to write
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+ * @lock: true if to take and release semaphore
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*
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* Performs byte write operation to SFP module's EEPROM over I2C interface at
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* a specified device address.
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- **/
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-s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
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- u8 dev_addr, u8 data)
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+ */
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+static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
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+ u8 dev_addr, u8 data, bool lock)
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{
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s32 status;
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u32 max_retry = 1;
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u32 retry = 0;
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u32 swfw_mask = hw->phy.phy_semaphore_mask;
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- if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
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+ if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
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return IXGBE_ERR_SWFW_SYNC;
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do {
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@@ -1788,7 +1896,9 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
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goto fail;
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ixgbe_i2c_stop(hw);
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- break;
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+ if (lock)
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+ hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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+ return 0;
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fail:
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ixgbe_i2c_bus_clear(hw);
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@@ -1799,21 +1909,57 @@ fail:
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hw_dbg(hw, "I2C byte write error.\n");
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} while (retry < max_retry);
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- hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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+ if (lock)
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+ hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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return status;
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}
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+/**
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+ * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
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+ * @hw: pointer to hardware structure
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+ * @byte_offset: byte offset to write
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+ * @data: value to write
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+ *
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+ * Performs byte write operation to SFP module's EEPROM over I2C interface at
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+ * a specified device address.
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+ */
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+s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
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+ u8 dev_addr, u8 data)
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+{
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+ return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
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+ data, true);
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+}
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+
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+/**
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+ * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
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+ * @hw: pointer to hardware structure
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+ * @byte_offset: byte offset to write
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+ * @data: value to write
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+ *
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+ * Performs byte write operation to SFP module's EEPROM over I2C interface at
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+ * a specified device address.
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+ */
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+s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
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+ u8 dev_addr, u8 data)
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+{
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+ return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
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+ data, false);
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+}
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+
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/**
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* ixgbe_i2c_start - Sets I2C start condition
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* @hw: pointer to hardware structure
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*
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* Sets I2C start condition (High -> Low on SDA while SCL is High)
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+ * Set bit-bang mode on X550 hardware.
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**/
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static void ixgbe_i2c_start(struct ixgbe_hw *hw)
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{
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u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
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+ i2cctl |= IXGBE_I2C_BB_EN(hw);
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+
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/* Start condition must begin with data and clock high */
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ixgbe_set_i2c_data(hw, &i2cctl, 1);
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ixgbe_raise_i2c_clk(hw, &i2cctl);
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@@ -1838,10 +1984,15 @@ static void ixgbe_i2c_start(struct ixgbe_hw *hw)
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* @hw: pointer to hardware structure
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*
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* Sets I2C stop condition (Low -> High on SDA while SCL is High)
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+ * Disables bit-bang mode and negates data output enable on X550
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+ * hardware.
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**/
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static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
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{
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u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
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+ u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
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+ u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
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+ u32 bb_en_bit = IXGBE_I2C_BB_EN(hw);
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/* Stop condition must begin with data low and clock high */
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ixgbe_set_i2c_data(hw, &i2cctl, 0);
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@@ -1854,6 +2005,13 @@ static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
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/* bus free time between stop and start (4.7us)*/
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udelay(IXGBE_I2C_T_BUF);
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+
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+ if (bb_en_bit || data_oe_bit || clk_oe_bit) {
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+ i2cctl &= ~bb_en_bit;
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+ i2cctl |= data_oe_bit | clk_oe_bit;
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+ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
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+ IXGBE_WRITE_FLUSH(hw);
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+ }
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}
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/**
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@@ -1901,6 +2059,7 @@ static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
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/* Release SDA line (set high) */
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i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
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i2cctl |= IXGBE_I2C_DATA_OUT(hw);
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+ i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw);
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IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
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IXGBE_WRITE_FLUSH(hw);
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@@ -1915,15 +2074,21 @@ static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
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**/
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static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
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{
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+ u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
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s32 status = 0;
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u32 i = 0;
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u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
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u32 timeout = 10;
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bool ack = true;
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+ if (data_oe_bit) {
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+ i2cctl |= IXGBE_I2C_DATA_OUT(hw);
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+ i2cctl |= data_oe_bit;
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+ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
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+ IXGBE_WRITE_FLUSH(hw);
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+ }
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ixgbe_raise_i2c_clk(hw, &i2cctl);
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-
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/* Minimum high period of clock is 4us */
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udelay(IXGBE_I2C_T_HIGH);
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@@ -1961,7 +2126,14 @@ static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
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static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
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|
{
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u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
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|
+ u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
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|
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+ if (data_oe_bit) {
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|
+ i2cctl |= IXGBE_I2C_DATA_OUT(hw);
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+ i2cctl |= data_oe_bit;
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|
+ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
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|
+ IXGBE_WRITE_FLUSH(hw);
|
|
|
+ }
|
|
|
ixgbe_raise_i2c_clk(hw, &i2cctl);
|
|
|
|
|
|
/* Minimum high period of clock is 4us */
|
|
@@ -2016,13 +2188,20 @@ static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
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* @i2cctl: Current value of I2CCTL register
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|
|
*
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|
* Raises the I2C clock line '0'->'1'
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|
|
+ * Negates the I2C clock output enable on X550 hardware.
|
|
|
**/
|
|
|
static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
|
|
|
{
|
|
|
+ u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
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|
|
u32 i = 0;
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|
|
u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
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|
|
u32 i2cctl_r = 0;
|
|
|
|
|
|
+ if (clk_oe_bit) {
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|
|
+ *i2cctl |= clk_oe_bit;
|
|
|
+ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
|
|
|
+ }
|
|
|
+
|
|
|
for (i = 0; i < timeout; i++) {
|
|
|
*i2cctl |= IXGBE_I2C_CLK_OUT(hw);
|
|
|
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
|
|
@@ -2042,11 +2221,13 @@ static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
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|
|
* @i2cctl: Current value of I2CCTL register
|
|
|
*
|
|
|
* Lowers the I2C clock line '1'->'0'
|
|
|
+ * Asserts the I2C clock output enable on X550 hardware.
|
|
|
**/
|
|
|
static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
|
|
|
{
|
|
|
|
|
|
*i2cctl &= ~IXGBE_I2C_CLK_OUT(hw);
|
|
|
+ *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw);
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|
|
|
|
|
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
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|
|
IXGBE_WRITE_FLUSH(hw);
|
|
@@ -2062,13 +2243,17 @@ static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
|
|
|
* @data: I2C data value (0 or 1) to set
|
|
|
*
|
|
|
* Sets the I2C data bit
|
|
|
+ * Asserts the I2C data output enable on X550 hardware.
|
|
|
**/
|
|
|
static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
|
|
|
{
|
|
|
+ u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
|
|
|
+
|
|
|
if (data)
|
|
|
*i2cctl |= IXGBE_I2C_DATA_OUT(hw);
|
|
|
else
|
|
|
*i2cctl &= ~IXGBE_I2C_DATA_OUT(hw);
|
|
|
+ *i2cctl &= ~data_oe_bit;
|
|
|
|
|
|
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
|
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
@@ -2076,6 +2261,14 @@ static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
|
|
|
/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
|
|
|
udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
|
|
|
|
|
|
+ if (!data) /* Can't verify data in this case */
|
|
|
+ return 0;
|
|
|
+ if (data_oe_bit) {
|
|
|
+ *i2cctl |= data_oe_bit;
|
|
|
+ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
|
|
|
+ IXGBE_WRITE_FLUSH(hw);
|
|
|
+ }
|
|
|
+
|
|
|
/* Verify data was set correctly */
|
|
|
*i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
|
|
|
if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
|
|
@@ -2092,9 +2285,19 @@ static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
|
|
|
* @i2cctl: Current value of I2CCTL register
|
|
|
*
|
|
|
* Returns the I2C data bit value
|
|
|
+ * Negates the I2C data output enable on X550 hardware.
|
|
|
**/
|
|
|
static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
|
|
|
{
|
|
|
+ u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
|
|
|
+
|
|
|
+ if (data_oe_bit) {
|
|
|
+ *i2cctl |= data_oe_bit;
|
|
|
+ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
|
|
|
+ IXGBE_WRITE_FLUSH(hw);
|
|
|
+ udelay(IXGBE_I2C_T_FALL);
|
|
|
+ }
|
|
|
+
|
|
|
if (*i2cctl & IXGBE_I2C_DATA_IN(hw))
|
|
|
return true;
|
|
|
return false;
|
|
@@ -2109,10 +2312,11 @@ static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
|
|
|
**/
|
|
|
static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
|
|
|
{
|
|
|
- u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
|
|
|
+ u32 i2cctl;
|
|
|
u32 i;
|
|
|
|
|
|
ixgbe_i2c_start(hw);
|
|
|
+ i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
|
|
|
|
|
|
ixgbe_set_i2c_data(hw, &i2cctl, 1);
|
|
|
|