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@@ -1088,7 +1088,7 @@ void RFSynthesizer_initial(struct hw_data *pHwData)
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msleep(5);
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msleep(5);
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ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F << 20) | 0xF01A0, 20);
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ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F << 20) | 0xF01A0, 20);
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- Wb35Reg_WriteSync(pHwData, 0x0864, ltmp) ;
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+ Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
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Wb35Reg_WriteSync(pHwData, 0x105c, pHwData->reg.BB5C);
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Wb35Reg_WriteSync(pHwData, 0x105c, pHwData->reg.BB5C);
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pHwData->reg.BB50 &= ~0x13; /* (MASK_IQCAL_MODE|MASK_CALIB_START); */
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pHwData->reg.BB50 &= ~0x13; /* (MASK_IQCAL_MODE|MASK_CALIB_START); */
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@@ -2096,7 +2096,7 @@ void Mxx_initial(struct hw_data *pHwData)
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pltmp[5] = reg->M38_MacControl;
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pltmp[5] = reg->M38_MacControl;
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/* M3C */
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/* M3C */
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- tmp = (DEFAULT_PIFST << 26) | (DEFAULT_EIFST << 16) | (DEFAULT_DIFST << 8) | (DEFAULT_SIFST << 4) | DEFAULT_OSIFST ;
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+ tmp = (DEFAULT_PIFST << 26) | (DEFAULT_EIFST << 16) | (DEFAULT_DIFST << 8) | (DEFAULT_SIFST << 4) | DEFAULT_OSIFST;
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reg->M3C_MacControl = tmp;
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reg->M3C_MacControl = tmp;
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pltmp[6] = tmp;
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pltmp[6] = tmp;
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