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@@ -5919,7 +5919,7 @@ static void rtl_hw_start_8411(struct rtl8169_private *tp)
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rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
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}
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-static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
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+static void rtl_hw_start_8168g(struct rtl8169_private *tp)
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{
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void __iomem *ioaddr = tp->mmio_addr;
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struct pci_dev *pdev = tp->pci_dev;
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@@ -5954,6 +5954,24 @@ static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
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rtl_pcie_state_l2l3_enable(tp, false);
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}
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+static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
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+{
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+ void __iomem *ioaddr = tp->mmio_addr;
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+ static const struct ephy_info e_info_8168g_1[] = {
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+ { 0x00, 0x0000, 0x0008 },
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+ { 0x0c, 0x37d0, 0x0820 },
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+ { 0x1e, 0x0000, 0x0001 },
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+ { 0x19, 0x8000, 0x0000 }
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+ };
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+
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+ rtl_hw_start_8168g(tp);
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+
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+ /* disable aspm and clock request before access ephy */
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+ RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
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+ RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
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+ rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
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+}
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+
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static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
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{
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void __iomem *ioaddr = tp->mmio_addr;
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@@ -5964,7 +5982,7 @@ static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
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{ 0x1e, 0xffff, 0x20eb }
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};
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- rtl_hw_start_8168g_1(tp);
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+ rtl_hw_start_8168g(tp);
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/* disable aspm and clock request before access ephy */
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RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
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@@ -5983,7 +6001,7 @@ static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
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{ 0x1e, 0x0000, 0x2000 }
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};
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- rtl_hw_start_8168g_1(tp);
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+ rtl_hw_start_8168g(tp);
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/* disable aspm and clock request before access ephy */
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RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
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