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@@ -2468,32 +2468,6 @@ static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
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dwc3_writel(dwc->regs, DWC3_DCFG, reg);
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}
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-static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
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-{
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- u32 reg;
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- u32 usb30_clock = DWC3_GCTL_CLK_BUS;
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-
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- /*
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- * We change the clock only at SS but I dunno why I would want to do
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- * this. Maybe it becomes part of the power saving plan.
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- */
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-
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- if ((speed != DWC3_DSTS_SUPERSPEED) &&
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- (speed != DWC3_DSTS_SUPERSPEED_PLUS))
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- return;
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-
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- /*
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- * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
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- * each time on Connect Done.
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- */
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- if (!usb30_clock)
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- return;
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-
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- reg = dwc3_readl(dwc->regs, DWC3_GCTL);
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- reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
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- dwc3_writel(dwc->regs, DWC3_GCTL, reg);
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-}
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-
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static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
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{
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struct dwc3_ep *dep;
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@@ -2505,7 +2479,14 @@ static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
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speed = reg & DWC3_DSTS_CONNECTSPD;
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dwc->speed = speed;
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- dwc3_update_ram_clk_sel(dwc, speed);
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+ /*
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+ * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
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+ * each time on Connect Done.
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+ *
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+ * Currently we always use the reset value. If any platform
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+ * wants to set this to a different value, we need to add a
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+ * setting and update GCTL.RAMCLKSEL here.
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+ */
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switch (speed) {
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case DWC3_DSTS_SUPERSPEED_PLUS:
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