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@@ -67,14 +67,14 @@
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* only the SRX bit set, it means that all of the data has been received
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* (once what's in the fifo has been read). However, depending on timing
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* an interrupt status with only the SRX bit set may not be recived. In
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- * those cases, the timeout mechanism is used to wait 5 ms in case more
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- * data arrives. After 5 ms, it is assumed that all of the data has been
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+ * those cases, the timeout mechanism is used to wait 20 ms in case more
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+ * data arrives. After 20 ms, it is assumed that all of the data has been
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* received and the accumulated rx data is sent upstream. The
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* 'TRF7970A_ST_WAIT_FOR_RX_DATA_CONT' state is used for this purpose
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* (i.e., it indicates that some data has been received but we're not sure
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* if there is more coming so a timeout in this state means all data has
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- * been received and there isn't an error). The delay is 5 ms since delays
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- * over 2 ms have been observed during testing (a little extra just in case).
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+ * been received and there isn't an error). The delay is 20 ms since delays
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+ * of ~16 ms have been observed during testing.
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*
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* Type 2 write and sector select commands respond with a 4-bit ACK or NACK.
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* Having only 4 bits in the FIFO won't normally generate an interrupt so
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@@ -120,7 +120,7 @@
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/* TX length is 3 nibbles long ==> 4KB - 1 bytes max */
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#define TRF7970A_TX_MAX (4096 - 1)
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-#define TRF7970A_WAIT_FOR_RX_DATA_TIMEOUT 5
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+#define TRF7970A_WAIT_FOR_RX_DATA_TIMEOUT 20
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#define TRF7970A_WAIT_FOR_FIFO_DRAIN_TIMEOUT 3
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#define TRF7970A_WAIT_TO_ISSUE_ISO15693_EOF 20
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