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@@ -2847,27 +2847,6 @@ static int tonga_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
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}
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}
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}
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}
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- /* Initialize Vddc DPM table based on allow Vddc values. And populate corresponding std values. */
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- for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
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- data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].vddc;
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- /* tonga_hwmgr->dpm_table.VddcTable.dpm_levels[i].param1 = stdVoltageTable->entries[i].Leakage; */
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- /* param1 is for corresponding std voltage */
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- data->dpm_table.vddc_table.dpm_levels[i].enabled = 1;
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- }
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- data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
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-
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- if (NULL != allowed_vdd_mclk_table) {
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- /* Initialize Vddci DPM table based on allow Mclk values */
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- for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
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- data->dpm_table.vdd_ci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].vddci;
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- data->dpm_table.vdd_ci_table.dpm_levels[i].enabled = 1;
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- data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].mvdd;
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- data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1;
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- }
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- data->dpm_table.vdd_ci_table.count = allowed_vdd_mclk_table->count;
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- data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
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- }
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-
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/* setup PCIE gen speed levels*/
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/* setup PCIE gen speed levels*/
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tonga_setup_default_pcie_tables(hwmgr);
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tonga_setup_default_pcie_tables(hwmgr);
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