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@@ -423,3 +423,33 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder)
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vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
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vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
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mutex_unlock(&dev_priv->sb_lock);
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mutex_unlock(&dev_priv->sb_lock);
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}
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}
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+
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+void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder)
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+{
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+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
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+ struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
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+ struct drm_device *dev = encoder->base.dev;
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+ struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
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+ enum dpio_channel port = vlv_dport_to_channel(dport);
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+ int pipe = intel_crtc->pipe;
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+ u32 val;
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+
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+ mutex_lock(&dev_priv->sb_lock);
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+
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+ /* Enable clock channels for this port */
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+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
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+ val = 0;
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+ if (pipe)
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+ val |= (1<<21);
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+ else
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+ val &= ~(1<<21);
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+ val |= 0x001000c4;
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+ vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
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+
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+ /* Program lane clock */
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+ vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
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+ vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
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+
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+ mutex_unlock(&dev_priv->sb_lock);
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+}
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