|
@@ -1089,18 +1089,20 @@ static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
|
|
|
struct arm_smmu_device *smmu = smmu_domain->smmu;
|
|
|
void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
|
|
|
|
|
|
- /* Devices in an IOMMU group may already be configured */
|
|
|
- ret = arm_smmu_master_configure_smrs(smmu, cfg);
|
|
|
- if (ret)
|
|
|
- return ret == -EEXIST ? 0 : ret;
|
|
|
-
|
|
|
/*
|
|
|
* FIXME: This won't be needed once we have IOMMU-backed DMA ops
|
|
|
- * for all devices behind the SMMU.
|
|
|
+ * for all devices behind the SMMU. Note that we need to take
|
|
|
+ * care configuring SMRs for devices both a platform_device and
|
|
|
+ * and a PCI device (i.e. a PCI host controller)
|
|
|
*/
|
|
|
if (smmu_domain->domain.type == IOMMU_DOMAIN_DMA)
|
|
|
return 0;
|
|
|
|
|
|
+ /* Devices in an IOMMU group may already be configured */
|
|
|
+ ret = arm_smmu_master_configure_smrs(smmu, cfg);
|
|
|
+ if (ret)
|
|
|
+ return ret == -EEXIST ? 0 : ret;
|
|
|
+
|
|
|
for (i = 0; i < cfg->num_streamids; ++i) {
|
|
|
u32 idx, s2cr;
|
|
|
|