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@@ -548,10 +548,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
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}
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}
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- ret = of_property_read_u32(np, "num-lanes", &pci->lanes);
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- if (ret)
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- pci->lanes = 0;
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-
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ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
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if (ret)
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pci->num_viewport = 2;
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@@ -748,13 +744,21 @@ static struct pci_ops dw_pcie_ops = {
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void dw_pcie_setup_rc(struct pcie_port *pp)
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{
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+ int ret;
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+ u32 lanes;
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u32 val;
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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+ struct device *dev = pci->dev;
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+ struct device_node *np = dev->of_node;
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+
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+ ret = of_property_read_u32(np, "num-lanes", &lanes);
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+ if (ret)
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+ lanes = 0;
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/* set the number of lanes */
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val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
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val &= ~PORT_LINK_MODE_MASK;
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- switch (pci->lanes) {
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+ switch (lanes) {
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case 1:
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val |= PORT_LINK_MODE_1_LANES;
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break;
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@@ -768,7 +772,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
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val |= PORT_LINK_MODE_8_LANES;
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break;
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default:
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- dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->lanes);
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+ dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
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return;
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}
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dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
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@@ -776,7 +780,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
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/* set link width speed control register */
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val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
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val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
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- switch (pci->lanes) {
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+ switch (lanes) {
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case 1:
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val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
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break;
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