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@@ -397,8 +397,7 @@ dtb_check_done:
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add sp, sp, r6
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add sp, sp, r6
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#endif
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#endif
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- tst r4, #1
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- bleq cache_clean_flush
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+ bl cache_clean_flush
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adr r0, BSYM(restart)
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adr r0, BSYM(restart)
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add r0, r0, r6
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add r0, r0, r6
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@@ -1047,6 +1046,8 @@ cache_clean_flush:
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b call_cache_fn
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b call_cache_fn
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__armv4_mpu_cache_flush:
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__armv4_mpu_cache_flush:
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+ tst r4, #1
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+ movne pc, lr
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mov r2, #1
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mov r2, #1
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mov r3, #0
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mov r3, #0
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mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
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mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
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@@ -1064,6 +1065,8 @@ __armv4_mpu_cache_flush:
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mov pc, lr
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mov pc, lr
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__fa526_cache_flush:
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__fa526_cache_flush:
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+ tst r4, #1
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+ movne pc, lr
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mov r1, #0
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mov r1, #0
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mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
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mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
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mcr p15, 0, r1, c7, c5, 0 @ flush I cache
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mcr p15, 0, r1, c7, c5, 0 @ flush I cache
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@@ -1072,13 +1075,16 @@ __fa526_cache_flush:
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__armv6_mmu_cache_flush:
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__armv6_mmu_cache_flush:
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mov r1, #0
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mov r1, #0
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- mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
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+ tst r4, #1
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+ mcreq p15, 0, r1, c7, c14, 0 @ clean+invalidate D
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mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
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mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
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- mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
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+ mcreq p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
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mcr p15, 0, r1, c7, c10, 4 @ drain WB
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mcr p15, 0, r1, c7, c10, 4 @ drain WB
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mov pc, lr
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mov pc, lr
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__armv7_mmu_cache_flush:
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__armv7_mmu_cache_flush:
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+ tst r4, #1
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+ bne iflush
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mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
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mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
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tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
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tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
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mov r10, #0
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mov r10, #0
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@@ -1139,6 +1145,8 @@ iflush:
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mov pc, lr
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mov pc, lr
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__armv5tej_mmu_cache_flush:
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__armv5tej_mmu_cache_flush:
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+ tst r4, #1
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+ movne pc, lr
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1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
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1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
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bne 1b
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bne 1b
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mcr p15, 0, r0, c7, c5, 0 @ flush I cache
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mcr p15, 0, r0, c7, c5, 0 @ flush I cache
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@@ -1146,6 +1154,8 @@ __armv5tej_mmu_cache_flush:
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mov pc, lr
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mov pc, lr
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__armv4_mmu_cache_flush:
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__armv4_mmu_cache_flush:
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+ tst r4, #1
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+ movne pc, lr
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mov r2, #64*1024 @ default: 32K dcache size (*2)
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mov r2, #64*1024 @ default: 32K dcache size (*2)
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mov r11, #32 @ default: 32 byte line size
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mov r11, #32 @ default: 32 byte line size
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mrc p15, 0, r3, c0, c0, 1 @ read cache type
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mrc p15, 0, r3, c0, c0, 1 @ read cache type
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@@ -1179,6 +1189,8 @@ no_cache_id:
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__armv3_mmu_cache_flush:
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__armv3_mmu_cache_flush:
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__armv3_mpu_cache_flush:
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__armv3_mpu_cache_flush:
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+ tst r4, #1
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+ movne pc, lr
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mov r1, #0
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mov r1, #0
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mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
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mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
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mov pc, lr
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mov pc, lr
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