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@@ -1118,34 +1118,34 @@ static int s5p_mfc_configure_2port_memory(struct s5p_mfc_dev *mfc_dev)
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* Create and initialize virtual devices for accessing
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* reserved memory regions.
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*/
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- mfc_dev->mem_dev[BANK1_CTX] = s5p_mfc_alloc_memdev(dev, "left",
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- BANK1_CTX);
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- if (!mfc_dev->mem_dev[BANK1_CTX])
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+ mfc_dev->mem_dev[BANK_L_CTX] = s5p_mfc_alloc_memdev(dev, "left",
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+ BANK_L_CTX);
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+ if (!mfc_dev->mem_dev[BANK_L_CTX])
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return -ENODEV;
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- mfc_dev->mem_dev[BANK2_CTX] = s5p_mfc_alloc_memdev(dev, "right",
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- BANK2_CTX);
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- if (!mfc_dev->mem_dev[BANK2_CTX]) {
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- device_unregister(mfc_dev->mem_dev[BANK1_CTX]);
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+ mfc_dev->mem_dev[BANK_R_CTX] = s5p_mfc_alloc_memdev(dev, "right",
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+ BANK_R_CTX);
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+ if (!mfc_dev->mem_dev[BANK_R_CTX]) {
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+ device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
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return -ENODEV;
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}
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/* Allocate memory for firmware and initialize both banks addresses */
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ret = s5p_mfc_alloc_firmware(mfc_dev);
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if (ret) {
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- device_unregister(mfc_dev->mem_dev[BANK2_CTX]);
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- device_unregister(mfc_dev->mem_dev[BANK1_CTX]);
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+ device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
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+ device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
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return ret;
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}
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- mfc_dev->dma_base[BANK1_CTX] = mfc_dev->fw_buf.dma;
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+ mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->fw_buf.dma;
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- bank2_virt = dma_alloc_coherent(mfc_dev->mem_dev[BANK2_CTX], align_size,
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- &bank2_dma_addr, GFP_KERNEL);
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+ bank2_virt = dma_alloc_coherent(mfc_dev->mem_dev[BANK_R_CTX],
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+ align_size, &bank2_dma_addr, GFP_KERNEL);
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if (!bank2_virt) {
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mfc_err("Allocating bank2 base failed\n");
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s5p_mfc_release_firmware(mfc_dev);
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- device_unregister(mfc_dev->mem_dev[BANK2_CTX]);
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- device_unregister(mfc_dev->mem_dev[BANK1_CTX]);
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+ device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
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+ device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
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return -ENOMEM;
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}
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@@ -1153,14 +1153,14 @@ static int s5p_mfc_configure_2port_memory(struct s5p_mfc_dev *mfc_dev)
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* should not have address of bank2 - MFC will treat it as a null frame.
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* To avoid such situation we set bank2 address below the pool address.
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*/
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- mfc_dev->dma_base[BANK2_CTX] = bank2_dma_addr - align_size;
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+ mfc_dev->dma_base[BANK_R_CTX] = bank2_dma_addr - align_size;
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- dma_free_coherent(mfc_dev->mem_dev[BANK2_CTX], align_size, bank2_virt,
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+ dma_free_coherent(mfc_dev->mem_dev[BANK_R_CTX], align_size, bank2_virt,
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bank2_dma_addr);
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- vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK1_CTX],
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+ vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX],
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DMA_BIT_MASK(32));
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- vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK2_CTX],
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+ vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX],
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DMA_BIT_MASK(32));
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return 0;
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@@ -1168,10 +1168,10 @@ static int s5p_mfc_configure_2port_memory(struct s5p_mfc_dev *mfc_dev)
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static void s5p_mfc_unconfigure_2port_memory(struct s5p_mfc_dev *mfc_dev)
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{
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- device_unregister(mfc_dev->mem_dev[BANK1_CTX]);
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- device_unregister(mfc_dev->mem_dev[BANK2_CTX]);
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- vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK1_CTX]);
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- vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK2_CTX]);
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+ device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
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+ device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
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+ vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX]);
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+ vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX]);
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}
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static int s5p_mfc_configure_common_memory(struct s5p_mfc_dev *mfc_dev)
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@@ -1201,8 +1201,8 @@ static int s5p_mfc_configure_common_memory(struct s5p_mfc_dev *mfc_dev)
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return -ENOMEM;
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}
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mfc_dev->mem_size = mem_size;
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- mfc_dev->dma_base[BANK1_CTX] = mfc_dev->mem_base;
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- mfc_dev->dma_base[BANK2_CTX] = mfc_dev->mem_base;
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+ mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->mem_base;
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+ mfc_dev->dma_base[BANK_R_CTX] = mfc_dev->mem_base;
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/*
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* MFC hardware cannot handle 0 as a base address, so mark first 128K
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@@ -1212,14 +1212,14 @@ static int s5p_mfc_configure_common_memory(struct s5p_mfc_dev *mfc_dev)
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unsigned int offset = 1 << MFC_BASE_ALIGN_ORDER;
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bitmap_set(mfc_dev->mem_bitmap, 0, offset >> PAGE_SHIFT);
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- mfc_dev->dma_base[BANK1_CTX] += offset;
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- mfc_dev->dma_base[BANK2_CTX] += offset;
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+ mfc_dev->dma_base[BANK_L_CTX] += offset;
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+ mfc_dev->dma_base[BANK_R_CTX] += offset;
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}
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/* Firmware allocation cannot fail in this case */
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s5p_mfc_alloc_firmware(mfc_dev);
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- mfc_dev->mem_dev[BANK1_CTX] = mfc_dev->mem_dev[BANK2_CTX] = dev;
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+ mfc_dev->mem_dev[BANK_L_CTX] = mfc_dev->mem_dev[BANK_R_CTX] = dev;
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vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
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dev_info(dev, "preallocated %ld MiB buffer for the firmware and context buffers\n",
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