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@@ -34,10 +34,6 @@
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#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
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#define MPIC_GREG_GCONF_MCK 0x08000000
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#define MPIC_GREG_GLOBAL_CONF_1 0x00030
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-#define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000
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-#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000
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-#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r) \
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- (((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
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#define MPIC_GREG_VENDOR_0 0x00040
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#define MPIC_GREG_VENDOR_1 0x00050
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#define MPIC_GREG_VENDOR_2 0x00060
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@@ -395,16 +391,6 @@ extern struct bus_type mpic_subsys;
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#define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */
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#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */
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-/* Get the version of primary MPIC */
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-#ifdef CONFIG_MPIC
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-extern u32 fsl_mpic_primary_get_version(void);
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-#else
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-static inline u32 fsl_mpic_primary_get_version(void)
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-{
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- return 0;
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-}
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-#endif
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-
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/* Allocate the controller structure and setup the linux irq descs
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* for the range if interrupts passed in. No HW initialization is
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* actually performed.
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@@ -496,11 +482,5 @@ extern unsigned int mpic_get_coreint_irq(void);
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/* Fetch Machine Check interrupt from primary mpic */
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extern unsigned int mpic_get_mcirq(void);
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-/* Set the EPIC clock ratio */
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-void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
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-
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-/* Enable/Disable EPIC serial interrupt mode */
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-void mpic_set_serial_int(struct mpic *mpic, int enable);
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-
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_MPIC_H */
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