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@@ -23,6 +23,7 @@
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*/
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#define SARL 0 /* Low part [0:31] */
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+#define SARL_A370_SSCG_ENABLE BIT(10)
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#define SARL_A370_PCLK_FREQ_OPT 11
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#define SARL_A370_PCLK_FREQ_OPT_MASK 0xF
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#define SARL_A370_FAB_FREQ_OPT 15
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@@ -133,10 +134,17 @@ static void __init a370_get_clk_ratio(
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}
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}
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+static bool a370_is_sscg_enabled(void __iomem *sar)
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+{
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+ return !(readl(sar) & SARL_A370_SSCG_ENABLE);
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+}
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+
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static const struct coreclk_soc_desc a370_coreclks = {
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.get_tclk_freq = a370_get_tclk_freq,
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.get_cpu_freq = a370_get_cpu_freq,
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.get_clk_ratio = a370_get_clk_ratio,
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+ .is_sscg_enabled = a370_is_sscg_enabled,
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+ .fix_sscg_deviation = kirkwood_fix_sscg_deviation,
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.ratios = a370_coreclk_ratios,
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.num_ratios = ARRAY_SIZE(a370_coreclk_ratios),
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};
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