Add the PMU so we can get proper perf event support on this SoC. Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
@@ -115,6 +115,11 @@
method = "smc";
};
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,