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@@ -336,6 +336,13 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
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apic_write(APIC_LVTT, lvtt_value);
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apic_write(APIC_LVTT, lvtt_value);
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if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
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if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
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+ /*
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+ * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
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+ * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
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+ * According to Intel, MFENCE can do the serialization here.
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+ */
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+ asm volatile("mfence" : : : "memory");
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+
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printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
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printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
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return;
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return;
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}
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}
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