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@@ -37,6 +37,7 @@
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#define GPIO_INTTYPE_LEVEL 0x38
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#define GPIO_INTTYPE_LEVEL 0x38
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#define GPIO_INT_POLARITY 0x3c
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#define GPIO_INT_POLARITY 0x3c
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#define GPIO_INTSTATUS 0x40
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#define GPIO_INTSTATUS 0x40
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+#define GPIO_PORTA_DEBOUNCE 0x48
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#define GPIO_PORTA_EOI 0x4c
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#define GPIO_PORTA_EOI 0x4c
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#define GPIO_EXT_PORTA 0x50
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#define GPIO_EXT_PORTA 0x50
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#define GPIO_EXT_PORTB 0x54
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#define GPIO_EXT_PORTB 0x54
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@@ -64,6 +65,12 @@ struct dwapb_gpio {
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struct irq_domain *domain;
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struct irq_domain *domain;
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};
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};
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+static inline struct dwapb_gpio_port *
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+to_dwapb_gpio_port(struct bgpio_chip *bgc)
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+{
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+ return container_of(bgc, struct dwapb_gpio_port, bgc);
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+}
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+
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static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
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static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
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{
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{
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struct bgpio_chip *bgc = &gpio->ports[0].bgc;
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struct bgpio_chip *bgc = &gpio->ports[0].bgc;
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@@ -84,8 +91,7 @@ static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
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static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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{
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struct bgpio_chip *bgc = to_bgpio_chip(gc);
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struct bgpio_chip *bgc = to_bgpio_chip(gc);
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- struct dwapb_gpio_port *port = container_of(bgc, struct
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- dwapb_gpio_port, bgc);
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+ struct dwapb_gpio_port *port = to_dwapb_gpio_port(bgc);
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struct dwapb_gpio *gpio = port->gpio;
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struct dwapb_gpio *gpio = port->gpio;
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return irq_find_mapping(gpio->domain, offset);
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return irq_find_mapping(gpio->domain, offset);
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@@ -235,6 +241,28 @@ static int dwapb_irq_set_type(struct irq_data *d, u32 type)
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return 0;
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return 0;
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}
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}
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+static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
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+ unsigned offset, unsigned debounce)
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+{
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+ struct bgpio_chip *bgc = to_bgpio_chip(gc);
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+ struct dwapb_gpio_port *port = to_dwapb_gpio_port(bgc);
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+ struct dwapb_gpio *gpio = port->gpio;
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+ unsigned long flags, val_deb;
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+ unsigned long mask = bgc->pin2mask(bgc, offset);
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+
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+ spin_lock_irqsave(&bgc->lock, flags);
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+
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+ val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
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+ if (debounce)
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+ dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask);
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+ else
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+ dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);
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+
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+ spin_unlock_irqrestore(&bgc->lock, flags);
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+
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+ return 0;
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+}
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+
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static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
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static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
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{
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{
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u32 worked;
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u32 worked;
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@@ -373,6 +401,10 @@ static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
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port->bgc.gc.ngpio = pp->ngpio;
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port->bgc.gc.ngpio = pp->ngpio;
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port->bgc.gc.base = pp->gpio_base;
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port->bgc.gc.base = pp->gpio_base;
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+ /* Only port A support debounce */
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+ if (pp->idx == 0)
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+ port->bgc.gc.set_debounce = dwapb_gpio_set_debounce;
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+
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if (pp->irq)
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if (pp->irq)
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dwapb_configure_irqs(gpio, port, pp);
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dwapb_configure_irqs(gpio, port, pp);
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