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@@ -140,10 +140,11 @@ static inline bool xilinx_pcie_link_is_up(struct xilinx_pcie_port *port)
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*/
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static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port)
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{
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+ struct device *dev = port->dev;
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unsigned long val = pcie_read(port, XILINX_PCIE_REG_RPEFR);
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if (val & XILINX_PCIE_RPEFR_ERR_VALID) {
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- dev_dbg(port->dev, "Requester ID %lu\n",
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+ dev_dbg(dev, "Requester ID %lu\n",
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val & XILINX_PCIE_RPEFR_REQ_ID);
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pcie_write(port, XILINX_PCIE_RPEFR_ALL_MASK,
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XILINX_PCIE_REG_RPEFR);
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@@ -383,6 +384,7 @@ static const struct irq_domain_ops intx_domain_ops = {
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static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
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{
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struct xilinx_pcie_port *port = (struct xilinx_pcie_port *)data;
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+ struct device *dev = port->dev;
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u32 val, mask, status, msi_data;
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/* Read interrupt decode and mask registers */
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@@ -394,32 +396,32 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
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return IRQ_NONE;
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if (status & XILINX_PCIE_INTR_LINK_DOWN)
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- dev_warn(port->dev, "Link Down\n");
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+ dev_warn(dev, "Link Down\n");
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if (status & XILINX_PCIE_INTR_ECRC_ERR)
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- dev_warn(port->dev, "ECRC failed\n");
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+ dev_warn(dev, "ECRC failed\n");
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if (status & XILINX_PCIE_INTR_STR_ERR)
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- dev_warn(port->dev, "Streaming error\n");
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+ dev_warn(dev, "Streaming error\n");
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if (status & XILINX_PCIE_INTR_HOT_RESET)
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- dev_info(port->dev, "Hot reset\n");
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+ dev_info(dev, "Hot reset\n");
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if (status & XILINX_PCIE_INTR_CFG_TIMEOUT)
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- dev_warn(port->dev, "ECAM access timeout\n");
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+ dev_warn(dev, "ECAM access timeout\n");
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if (status & XILINX_PCIE_INTR_CORRECTABLE) {
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- dev_warn(port->dev, "Correctable error message\n");
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+ dev_warn(dev, "Correctable error message\n");
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xilinx_pcie_clear_err_interrupts(port);
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}
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if (status & XILINX_PCIE_INTR_NONFATAL) {
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- dev_warn(port->dev, "Non fatal error message\n");
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+ dev_warn(dev, "Non fatal error message\n");
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xilinx_pcie_clear_err_interrupts(port);
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}
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if (status & XILINX_PCIE_INTR_FATAL) {
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- dev_warn(port->dev, "Fatal error message\n");
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+ dev_warn(dev, "Fatal error message\n");
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xilinx_pcie_clear_err_interrupts(port);
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}
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@@ -429,7 +431,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
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/* Check whether interrupt valid */
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if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
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- dev_warn(port->dev, "RP Intr FIFO1 read error\n");
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+ dev_warn(dev, "RP Intr FIFO1 read error\n");
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goto error;
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}
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@@ -451,7 +453,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
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val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
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if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
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- dev_warn(port->dev, "RP Intr FIFO1 read error\n");
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+ dev_warn(dev, "RP Intr FIFO1 read error\n");
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goto error;
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}
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@@ -471,31 +473,31 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
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}
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if (status & XILINX_PCIE_INTR_SLV_UNSUPP)
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- dev_warn(port->dev, "Slave unsupported request\n");
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+ dev_warn(dev, "Slave unsupported request\n");
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if (status & XILINX_PCIE_INTR_SLV_UNEXP)
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- dev_warn(port->dev, "Slave unexpected completion\n");
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+ dev_warn(dev, "Slave unexpected completion\n");
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if (status & XILINX_PCIE_INTR_SLV_COMPL)
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- dev_warn(port->dev, "Slave completion timeout\n");
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+ dev_warn(dev, "Slave completion timeout\n");
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if (status & XILINX_PCIE_INTR_SLV_ERRP)
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- dev_warn(port->dev, "Slave Error Poison\n");
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+ dev_warn(dev, "Slave Error Poison\n");
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if (status & XILINX_PCIE_INTR_SLV_CMPABT)
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- dev_warn(port->dev, "Slave Completer Abort\n");
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+ dev_warn(dev, "Slave Completer Abort\n");
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if (status & XILINX_PCIE_INTR_SLV_ILLBUR)
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- dev_warn(port->dev, "Slave Illegal Burst\n");
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+ dev_warn(dev, "Slave Illegal Burst\n");
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if (status & XILINX_PCIE_INTR_MST_DECERR)
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- dev_warn(port->dev, "Master decode error\n");
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+ dev_warn(dev, "Master decode error\n");
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if (status & XILINX_PCIE_INTR_MST_SLVERR)
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- dev_warn(port->dev, "Master slave error\n");
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+ dev_warn(dev, "Master slave error\n");
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if (status & XILINX_PCIE_INTR_MST_ERRP)
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- dev_warn(port->dev, "Master error poison\n");
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+ dev_warn(dev, "Master error poison\n");
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error:
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/* Clear the Interrupt Decode register */
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@@ -554,10 +556,12 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
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*/
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static void xilinx_pcie_init_port(struct xilinx_pcie_port *port)
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{
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+ struct device *dev = port->dev;
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+
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if (xilinx_pcie_link_is_up(port))
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- dev_info(port->dev, "PCIe Link is UP\n");
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+ dev_info(dev, "PCIe Link is UP\n");
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else
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- dev_info(port->dev, "PCIe Link is DOWN\n");
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+ dev_info(dev, "PCIe Link is DOWN\n");
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/* Disable all interrupts */
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pcie_write(port, ~XILINX_PCIE_IDR_ALL_MASK,
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@@ -627,8 +631,8 @@ static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)
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*/
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static int xilinx_pcie_probe(struct platform_device *pdev)
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{
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- struct xilinx_pcie_port *port;
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struct device *dev = &pdev->dev;
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+ struct xilinx_pcie_port *port;
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struct pci_bus *bus;
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int err;
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resource_size_t iobase = 0;
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@@ -668,15 +672,14 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
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if (err)
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goto error;
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- bus = pci_create_root_bus(&pdev->dev, 0,
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- &xilinx_pcie_ops, port, &res);
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+ bus = pci_create_root_bus(dev, 0, &xilinx_pcie_ops, port, &res);
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if (!bus) {
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err = -ENOMEM;
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goto error;
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}
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#ifdef CONFIG_PCI_MSI
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- xilinx_pcie_msi_chip.dev = port->dev;
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+ xilinx_pcie_msi_chip.dev = dev;
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bus->msi = &xilinx_pcie_msi_chip;
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#endif
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pci_scan_child_bus(bus);
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