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@@ -69,6 +69,15 @@ static DEFINE_RAW_SPINLOCK(sh_tmu_lock);
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#define TCNT 1 /* channel register */
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#define TCR 2 /* channel register */
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+#define TCR_UNF (1 << 8)
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+#define TCR_UNIE (1 << 5)
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+#define TCR_TPSC_CLK4 (0 << 0)
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+#define TCR_TPSC_CLK16 (1 << 0)
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+#define TCR_TPSC_CLK64 (2 << 0)
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+#define TCR_TPSC_CLK256 (3 << 0)
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+#define TCR_TPSC_CLK1024 (4 << 0)
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+#define TCR_TPSC_MASK (7 << 0)
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+
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static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)
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{
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unsigned long offs;
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@@ -140,7 +149,7 @@ static int __sh_tmu_enable(struct sh_tmu_channel *ch)
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/* configure channel to parent clock / 4, irq off */
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ch->rate = clk_get_rate(ch->tmu->clk) / 4;
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- sh_tmu_write(ch, TCR, 0x0000);
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+ sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
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/* enable channel */
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sh_tmu_start_stop_ch(ch, 1);
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@@ -165,7 +174,7 @@ static void __sh_tmu_disable(struct sh_tmu_channel *ch)
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sh_tmu_start_stop_ch(ch, 0);
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/* disable interrupts in TMU block */
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- sh_tmu_write(ch, TCR, 0x0000);
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+ sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
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/* stop clock */
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clk_disable(ch->tmu->clk);
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@@ -195,7 +204,7 @@ static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
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sh_tmu_read(ch, TCR);
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/* enable interrupt */
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- sh_tmu_write(ch, TCR, 0x0020);
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+ sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
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/* reload delta value in case of periodic timer */
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if (periodic)
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@@ -215,9 +224,9 @@ static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
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/* disable or acknowledge interrupt */
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if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT)
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- sh_tmu_write(ch, TCR, 0x0000);
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+ sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
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else
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- sh_tmu_write(ch, TCR, 0x0020);
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+ sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
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/* notify clockevent layer */
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ch->ced.event_handler(&ch->ced);
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