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@@ -53,6 +53,15 @@ MODULE_PARM_DESC(pow_receive_group, "\n"
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"\tgroup. Also any other software can submit packets to this\n"
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"\tgroup for the kernel to process.");
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+static int receive_group_order;
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+module_param(receive_group_order, int, 0444);
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+MODULE_PARM_DESC(receive_group_order, "\n"
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+ "\tOrder (0..4) of receive groups to take into use. Ethernet hardware\n"
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+ "\twill be configured to send incoming packets to multiple POW\n"
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+ "\tgroups. pow_receive_group parameter is ignored when multiple\n"
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+ "\tgroups are taken into use and groups are allocated starting\n"
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+ "\tfrom 0. By default, a single group is used.\n");
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+
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int pow_send_group = -1;
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module_param(pow_send_group, int, 0644);
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MODULE_PARM_DESC(pow_send_group, "\n"
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@@ -680,7 +689,13 @@ static int cvm_oct_probe(struct platform_device *pdev)
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cvmx_helper_initialize_packet_io_global();
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- pow_receive_groups = BIT(pow_receive_group);
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+ if (receive_group_order) {
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+ if (receive_group_order > 4)
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+ receive_group_order = 4;
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+ pow_receive_groups = (1 << (1 << receive_group_order)) - 1;
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+ } else {
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+ pow_receive_groups = BIT(pow_receive_group);
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+ }
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/* Change the input group for all ports before input is enabled */
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num_interfaces = cvmx_helper_get_number_of_interfaces();
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@@ -695,7 +710,37 @@ static int cvm_oct_probe(struct platform_device *pdev)
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pip_prt_tagx.u64 =
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cvmx_read_csr(CVMX_PIP_PRT_TAGX(port));
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- pip_prt_tagx.s.grp = pow_receive_group;
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+
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+ if (receive_group_order) {
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+ int tag_mask;
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+
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+ /* We support only 16 groups at the moment, so
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+ * always disable the two additional "hidden"
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+ * tag_mask bits on CN68XX.
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+ */
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+ if (OCTEON_IS_MODEL(OCTEON_CN68XX))
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+ pip_prt_tagx.u64 |= 0x3ull << 44;
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+
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+ tag_mask = ~((1 << receive_group_order) - 1);
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+ pip_prt_tagx.s.grptagbase = 0;
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+ pip_prt_tagx.s.grptagmask = tag_mask;
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+ pip_prt_tagx.s.grptag = 1;
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+ pip_prt_tagx.s.tag_mode = 0;
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+ pip_prt_tagx.s.inc_prt_flag = 1;
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+ pip_prt_tagx.s.ip6_dprt_flag = 1;
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+ pip_prt_tagx.s.ip4_dprt_flag = 1;
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+ pip_prt_tagx.s.ip6_sprt_flag = 1;
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+ pip_prt_tagx.s.ip4_sprt_flag = 1;
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+ pip_prt_tagx.s.ip6_dst_flag = 1;
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+ pip_prt_tagx.s.ip4_dst_flag = 1;
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+ pip_prt_tagx.s.ip6_src_flag = 1;
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+ pip_prt_tagx.s.ip4_src_flag = 1;
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+ pip_prt_tagx.s.grp = 0;
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+ } else {
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+ pip_prt_tagx.s.grptag = 0;
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+ pip_prt_tagx.s.grp = pow_receive_group;
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+ }
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+
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cvmx_write_csr(CVMX_PIP_PRT_TAGX(port),
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pip_prt_tagx.u64);
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}
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