drm/nouveau/mmu: rename from vmmgr (no binary change)

Switch to NVIDIA's name for the device.

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/include/nvif/device.h

@@ -29,7 +29,7 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **);
 /*XXX*/
 #include <subdev/bios.h>
 #include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 #include <subdev/bar.h>
 #include <subdev/gpio.h>
 #include <subdev/clk.h>
@@ -40,7 +40,7 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **);
 #define nvkm_device(a) nv_device(nvkm_object((a)))
 #define nvkm_bios(a) nouveau_bios(nvkm_device(a))
 #define nvkm_fb(a) nouveau_fb(nvkm_device(a))
-#define nvkm_vmmgr(a) nouveau_vmmgr(nvkm_device(a))
+#define nvkm_mmu(a) nouveau_mmu(nvkm_device(a))
 #define nvkm_bar(a) nouveau_bar(nvkm_device(a))
 #define nvkm_gpio(a) nouveau_gpio(nvkm_device(a))
 #define nvkm_clk(a) nouveau_clk(nvkm_device(a))

drivers/gpu/drm/nouveau/include/nvkm/core/device.h

@@ -33,7 +33,7 @@ enum nv_subdev_type {
 	NVDEV_SUBDEV_FB,
 	NVDEV_SUBDEV_LTC,
 	NVDEV_SUBDEV_INSTMEM,
-	NVDEV_SUBDEV_VM,
+	NVDEV_SUBDEV_MMU,
 	NVDEV_SUBDEV_BAR,
 	NVDEV_SUBDEV_PMU,
 	NVDEV_SUBDEV_VOLT,

drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h

@@ -4,7 +4,7 @@
 #include <core/object.h>
 #include <core/gpuobj.h>
 
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 
 #define NV_ENGCTX_(eng,var) (NV_ENGCTX_CLASS | ((var) << 8) | (eng))
 #define NV_ENGCTX(name,var)  NV_ENGCTX_(NVDEV_ENGINE_##name, (var))

drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h

@@ -5,7 +5,7 @@
 #include <core/device.h>
 #include <core/mm.h>
 
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 
 /* memory type/access flags, do not match hardware values */
 #define NV_MEM_ACCESS_RO  1

drivers/gpu/drm/nouveau/include/nvkm/subdev/vm.h → drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h

@@ -22,8 +22,8 @@
  * Authors: Ben Skeggs
  */
 
-#ifndef __NOUVEAU_VM_H__
-#define __NOUVEAU_VM_H__
+#ifndef __NOUVEAU_MMU_H__
+#define __NOUVEAU_MMU_H__
 
 #include <core/object.h>
 #include <core/subdev.h>
@@ -53,7 +53,7 @@ struct nouveau_vma {
 };
 
 struct nouveau_vm {
-	struct nouveau_vmmgr *vmm;
+	struct nouveau_mmu *mmu;
 	struct nouveau_mm mm;
 	struct kref refcount;
 
@@ -65,7 +65,7 @@ struct nouveau_vm {
 	u32 lpde;
 };
 
-struct nouveau_vmmgr {
+struct nouveau_mmu {
 	struct nouveau_subdev base;
 
 	u64 limit;
@@ -74,7 +74,7 @@ struct nouveau_vmmgr {
 	u8  spg_shift;
 	u8  lpg_shift;
 
-	int  (*create)(struct nouveau_vmmgr *, u64 offset, u64 length,
+	int  (*create)(struct nouveau_mmu *, u64 offset, u64 length,
 		       u64 mm_offset, struct nouveau_vm **);
 
 	void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 pde,
@@ -88,37 +88,37 @@ struct nouveau_vmmgr {
 	void (*flush)(struct nouveau_vm *);
 };
 
-static inline struct nouveau_vmmgr *
-nouveau_vmmgr(void *obj)
+static inline struct nouveau_mmu *
+nouveau_mmu(void *obj)
 {
-	return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_VM);
+	return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_MMU);
 }
 
-#define nouveau_vmmgr_create(p,e,o,i,f,d)                                      \
+#define nouveau_mmu_create(p,e,o,i,f,d)                                      \
 	nouveau_subdev_create((p), (e), (o), 0, (i), (f), (d))
-#define nouveau_vmmgr_destroy(p)                                               \
+#define nouveau_mmu_destroy(p)                                               \
 	nouveau_subdev_destroy(&(p)->base)
-#define nouveau_vmmgr_init(p)                                                  \
+#define nouveau_mmu_init(p)                                                  \
 	nouveau_subdev_init(&(p)->base)
-#define nouveau_vmmgr_fini(p,s)                                                \
+#define nouveau_mmu_fini(p,s)                                                \
 	nouveau_subdev_fini(&(p)->base, (s))
 
-#define _nouveau_vmmgr_dtor _nouveau_subdev_dtor
-#define _nouveau_vmmgr_init _nouveau_subdev_init
-#define _nouveau_vmmgr_fini _nouveau_subdev_fini
+#define _nouveau_mmu_dtor _nouveau_subdev_dtor
+#define _nouveau_mmu_init _nouveau_subdev_init
+#define _nouveau_mmu_fini _nouveau_subdev_fini
 
-extern struct nouveau_oclass nv04_vmmgr_oclass;
-extern struct nouveau_oclass nv41_vmmgr_oclass;
-extern struct nouveau_oclass nv44_vmmgr_oclass;
-extern struct nouveau_oclass nv50_vmmgr_oclass;
-extern struct nouveau_oclass nvc0_vmmgr_oclass;
+extern struct nouveau_oclass nv04_mmu_oclass;
+extern struct nouveau_oclass nv41_mmu_oclass;
+extern struct nouveau_oclass nv44_mmu_oclass;
+extern struct nouveau_oclass nv50_mmu_oclass;
+extern struct nouveau_oclass nvc0_mmu_oclass;
 
-int  nv04_vm_create(struct nouveau_vmmgr *, u64, u64, u64,
+int  nv04_vm_create(struct nouveau_mmu *, u64, u64, u64,
 		    struct nouveau_vm **);
-void nv04_vmmgr_dtor(struct nouveau_object *);
+void nv04_mmu_dtor(struct nouveau_object *);
 
 /* nouveau_vm.c */
-int  nouveau_vm_create(struct nouveau_vmmgr *, u64 offset, u64 length,
+int  nouveau_vm_create(struct nouveau_mmu *, u64 offset, u64 length,
 		       u64 mm_offset, u32 block, struct nouveau_vm **);
 int  nouveau_vm_new(struct nouveau_device *, u64 offset, u64 length,
 		    u64 mm_offset, struct nouveau_vm **);

drivers/gpu/drm/nouveau/nouveau_bo.c

@@ -193,7 +193,7 @@ nouveau_bo_new(struct drm_device *dev, int size, int align,
 	int max_size;
 
 	if (drm->client.vm)
-		lpg_shift = drm->client.vm->vmm->lpg_shift;
+		lpg_shift = drm->client.vm->mmu->lpg_shift;
 	max_size = INT_MAX & ~((1 << lpg_shift) - 1);
 
 	if (size <= 0 || size > max_size) {
@@ -220,7 +220,7 @@ nouveau_bo_new(struct drm_device *dev, int size, int align,
 	nvbo->page_shift = 12;
 	if (drm->client.vm) {
 		if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
-			nvbo->page_shift = drm->client.vm->vmm->lpg_shift;
+			nvbo->page_shift = drm->client.vm->mmu->lpg_shift;
 	}
 
 	nouveau_bo_fixup_align(nvbo, flags, &align, &size);
@@ -1240,7 +1240,7 @@ nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
 	list_for_each_entry(vma, &nvbo->vma_list, head) {
 		if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM &&
 			      (new_mem->mem_type == TTM_PL_VRAM ||
-			       nvbo->page_shift != vma->vm->vmm->lpg_shift)) {
+			       nvbo->page_shift != vma->vm->mmu->lpg_shift)) {
 			nouveau_vm_map(vma, new_mem->mm_node);
 		} else {
 			nouveau_vm_unmap(vma);
@@ -1639,7 +1639,7 @@ nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
 
 	if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM &&
 	    (nvbo->bo.mem.mem_type == TTM_PL_VRAM ||
-	     nvbo->page_shift != vma->vm->vmm->lpg_shift))
+	     nvbo->page_shift != vma->vm->mmu->lpg_shift))
 		nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
 
 	list_add_tail(&vma->head, &nvbo->vma_list);

drivers/gpu/drm/nouveau/nouveau_chan.c

@@ -88,7 +88,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
 		     u32 handle, u32 size, struct nouveau_channel **pchan)
 {
 	struct nouveau_cli *cli = (void *)nvif_client(&device->base);
-	struct nouveau_vmmgr *vmm = nvkm_vmmgr(device);
+	struct nouveau_mmu *mmu = nvkm_mmu(device);
 	struct nv_dma_v0 args = {};
 	struct nouveau_channel *chan;
 	u32 target;
@@ -136,7 +136,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
 		args.target = NV_DMA_V0_TARGET_VM;
 		args.access = NV_DMA_V0_ACCESS_VM;
 		args.start = 0;
-		args.limit = cli->vm->vmm->limit - 1;
+		args.limit = cli->vm->mmu->limit - 1;
 	} else
 	if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) {
 		if (device->info.family == NV_DEVICE_INFO_V0_TNT) {
@@ -165,7 +165,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
 			args.target = NV_DMA_V0_TARGET_VM;
 			args.access = NV_DMA_V0_ACCESS_RDWR;
 			args.start = 0;
-			args.limit = vmm->limit - 1;
+			args.limit = mmu->limit - 1;
 		}
 	}
 
@@ -281,7 +281,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
 {
 	struct nvif_device *device = chan->device;
 	struct nouveau_cli *cli = (void *)nvif_client(&device->base);
-	struct nouveau_vmmgr *vmm = nvkm_vmmgr(device);
+	struct nouveau_mmu *mmu = nvkm_mmu(device);
 	struct nouveau_software_chan *swch;
 	struct nv_dma_v0 args = {};
 	int ret, i;
@@ -294,7 +294,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
 			args.target = NV_DMA_V0_TARGET_VM;
 			args.access = NV_DMA_V0_ACCESS_VM;
 			args.start = 0;
-			args.limit = cli->vm->vmm->limit - 1;
+			args.limit = cli->vm->mmu->limit - 1;
 		} else {
 			args.target = NV_DMA_V0_TARGET_VRAM;
 			args.access = NV_DMA_V0_ACCESS_RDWR;
@@ -312,7 +312,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
 			args.target = NV_DMA_V0_TARGET_VM;
 			args.access = NV_DMA_V0_ACCESS_VM;
 			args.start = 0;
-			args.limit = cli->vm->vmm->limit - 1;
+			args.limit = cli->vm->mmu->limit - 1;
 		} else
 		if (chan->drm->agp.stat == ENABLED) {
 			args.target = NV_DMA_V0_TARGET_AGP;
@@ -324,7 +324,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
 			args.target = NV_DMA_V0_TARGET_VM;
 			args.access = NV_DMA_V0_ACCESS_RDWR;
 			args.start = 0;
-			args.limit = vmm->limit - 1;
+			args.limit = mmu->limit - 1;
 		}
 
 		ret = nvif_object_init(chan->object, NULL, gart,

drivers/gpu/drm/nouveau/nouveau_display.h

@@ -1,7 +1,7 @@
 #ifndef __NOUVEAU_DISPLAY_H__
 #define __NOUVEAU_DISPLAY_H__
 
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 
 #include "nouveau_drm.h"
 

drivers/gpu/drm/nouveau/nouveau_ttm.c

@@ -203,13 +203,13 @@ const struct ttm_mem_type_manager_func nouveau_gart_manager = {
 };
 
 /*XXX*/
-#include <subdev/vm/nv04.h>
+#include <subdev/mmu/nv04.h>
 static int
 nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
 {
 	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
-	struct nouveau_vmmgr *vmm = nvkm_vmmgr(&drm->device);
-	struct nv04_vmmgr_priv *priv = (void *)vmm;
+	struct nouveau_mmu *mmu = nvkm_mmu(&drm->device);
+	struct nv04_mmu_priv *priv = (void *)mmu;
 	struct nouveau_vm *vm = NULL;
 	nouveau_vm_ref(priv->vm, &vm, NULL);
 	man->priv = vm;
@@ -354,7 +354,7 @@ nouveau_ttm_init(struct nouveau_drm *drm)
 	u32 bits;
 	int ret;
 
-	bits = nvkm_vmmgr(&drm->device)->dma_bits;
+	bits = nvkm_mmu(&drm->device)->dma_bits;
 	if (nv_device_is_pci(nvkm_device(&drm->device))) {
 		if (drm->agp.stat == ENABLED ||
 		     !pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits)))
@@ -401,7 +401,7 @@ nouveau_ttm_init(struct nouveau_drm *drm)
 
 	/* GART init */
 	if (drm->agp.stat != ENABLED) {
-		drm->gem.gart_available = nvkm_vmmgr(&drm->device)->limit;
+		drm->gem.gart_available = nvkm_mmu(&drm->device)->limit;
 	} else {
 		drm->gem.gart_available = drm->agp.size;
 	}

drivers/gpu/drm/nouveau/nvkm/core/engctx.c

@@ -28,7 +28,7 @@
 #include <core/client.h>
 #include <core/engctx.h>
 
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 
 static inline int
 nouveau_engctx_exists(struct nouveau_object *parent,

drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c

@@ -27,7 +27,7 @@
 
 #include <subdev/instmem.h>
 #include <subdev/bar.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 
 void
 nouveau_gpuobj_destroy(struct nouveau_gpuobj *gpuobj)

drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c

@@ -27,7 +27,7 @@
 #include <engine/copy.h>
 
 #include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 
 #include <core/client.h>
 #include <core/enum.h>

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

@@ -218,7 +218,7 @@ static const u64 disable_map[] = {
 	[NVDEV_SUBDEV_LTC]	= NV_DEVICE_V0_DISABLE_CORE,
 	[NVDEV_SUBDEV_IBUS]	= NV_DEVICE_V0_DISABLE_CORE,
 	[NVDEV_SUBDEV_INSTMEM]	= NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_SUBDEV_VM]	= NV_DEVICE_V0_DISABLE_CORE,
+	[NVDEV_SUBDEV_MMU]	= NV_DEVICE_V0_DISABLE_CORE,
 	[NVDEV_SUBDEV_BAR]	= NV_DEVICE_V0_DISABLE_CORE,
 	[NVDEV_SUBDEV_VOLT]	= NV_DEVICE_V0_DISABLE_CORE,
 	[NVDEV_SUBDEV_THERM]	= NV_DEVICE_V0_DISABLE_CORE,

drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c

@@ -37,7 +37,7 @@
 #include <subdev/ltc.h>
 #include <subdev/ibus.h>
 #include <subdev/instmem.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 #include <subdev/bar.h>
 #include <subdev/pmu.h>
 #include <subdev/volt.h>
@@ -75,7 +75,7 @@ gm100_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_LTC    ] =  gm107_ltc_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  nv108_pmu_oclass;
 
@@ -119,7 +119,7 @@ gm100_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_LTC    ] =  gm107_ltc_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  nv108_pmu_oclass;
 #if 0

drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c

@@ -31,7 +31,7 @@
 #include <subdev/timer.h>
 #include <subdev/fb.h>
 #include <subdev/instmem.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 
 #include <engine/device.h>
 #include <engine/dmaobj.h>
@@ -55,7 +55,7 @@ nv04_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv04_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv04_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv04_software_oclass;
@@ -73,7 +73,7 @@ nv04_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv04_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv04_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv04_software_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c

@@ -32,7 +32,7 @@
 #include <subdev/timer.h>
 #include <subdev/fb.h>
 #include <subdev/instmem.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 
 #include <engine/device.h>
 #include <engine/dmaobj.h>
@@ -57,7 +57,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
@@ -74,7 +74,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
@@ -93,7 +93,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
@@ -112,7 +112,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv1a_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
@@ -131,7 +131,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
@@ -150,7 +150,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
@@ -169,7 +169,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv1a_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
@@ -188,7 +188,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c

@@ -33,7 +33,7 @@
 #include <subdev/timer.h>
 #include <subdev/fb.h>
 #include <subdev/instmem.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 
 #include <engine/device.h>
 #include <engine/dmaobj.h>
@@ -58,7 +58,7 @@ nv20_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv20_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
@@ -77,7 +77,7 @@ nv20_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv25_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
@@ -96,7 +96,7 @@ nv20_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv25_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
@@ -115,7 +115,7 @@ nv20_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv25_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c

@@ -32,7 +32,7 @@
 #include <subdev/timer.h>
 #include <subdev/fb.h>
 #include <subdev/instmem.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 
 #include <engine/device.h>
 #include <engine/dmaobj.h>
@@ -58,7 +58,7 @@ nv30_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv30_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
@@ -77,7 +77,7 @@ nv30_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv35_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
@@ -96,7 +96,7 @@ nv30_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv30_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
@@ -116,7 +116,7 @@ nv30_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv36_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
@@ -136,7 +136,7 @@ nv30_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c

@@ -24,7 +24,7 @@
 
 #include <subdev/bios.h>
 #include <subdev/bus.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 #include <subdev/gpio.h>
 #include <subdev/i2c.h>
 #include <subdev/clk.h>
@@ -34,7 +34,7 @@
 #include <subdev/timer.h>
 #include <subdev/fb.h>
 #include <subdev/instmem.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 #include <subdev/volt.h>
 
 #include <engine/device.h>
@@ -63,7 +63,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv40_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
@@ -86,7 +86,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv41_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv41_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv41_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
@@ -109,7 +109,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv41_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv41_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv41_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
@@ -132,7 +132,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv41_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv41_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv41_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
@@ -155,7 +155,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv40_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
@@ -178,7 +178,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv47_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv41_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv41_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
@@ -201,7 +201,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv49_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv41_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv41_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
@@ -224,7 +224,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv49_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv41_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv41_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
@@ -247,7 +247,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv44_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv44_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
@@ -270,7 +270,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv46_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv44_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
@@ -293,7 +293,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv44_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv44_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
@@ -316,7 +316,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv46_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv44_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
@@ -339,7 +339,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv4e_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv44_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
@@ -362,7 +362,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv46_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv44_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
@@ -385,7 +385,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv46_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv44_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
@@ -408,7 +408,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv46_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv44_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c

@@ -35,7 +35,7 @@
 #include <subdev/timer.h>
 #include <subdev/fb.h>
 #include <subdev/instmem.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 #include <subdev/bar.h>
 #include <subdev/pmu.h>
 #include <subdev/volt.h>
@@ -73,7 +73,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv50_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
@@ -99,7 +99,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
@@ -128,7 +128,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
@@ -157,7 +157,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
@@ -186,7 +186,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
@@ -215,7 +215,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
@@ -244,7 +244,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
@@ -273,7 +273,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
@@ -302,7 +302,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nvaa_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
@@ -331,7 +331,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nvaa_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
@@ -360,7 +360,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nva3_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  nva3_pmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -391,7 +391,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nva3_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  nva3_pmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -421,7 +421,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nva3_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  nva3_pmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -451,7 +451,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] =  nvaf_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  nva3_pmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c

@@ -37,7 +37,7 @@
 #include <subdev/ltc.h>
 #include <subdev/ibus.h>
 #include <subdev/instmem.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 #include <subdev/bar.h>
 #include <subdev/pmu.h>
 #include <subdev/volt.h>
@@ -75,7 +75,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  nvc0_pmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -108,7 +108,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  nvc0_pmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -141,7 +141,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  nvc0_pmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -173,7 +173,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  nvc0_pmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -206,7 +206,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  nvc0_pmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -238,7 +238,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  nvc0_pmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -270,7 +270,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  nvc0_pmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -303,7 +303,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  nvd0_pmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -335,7 +335,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c

@@ -37,7 +37,7 @@
 #include <subdev/ltc.h>
 #include <subdev/ibus.h>
 #include <subdev/instmem.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 #include <subdev/bar.h>
 #include <subdev/pmu.h>
 #include <subdev/volt.h>
@@ -75,7 +75,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  gk104_pmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -109,7 +109,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  nvd0_pmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -143,7 +143,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  gk104_pmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -171,7 +171,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &gk20a_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &gk20a_bar_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk20a_fifo_oclass;
@@ -199,7 +199,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  nvd0_pmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -233,7 +233,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  nvd0_pmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -267,7 +267,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  nv108_pmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -300,7 +300,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_SUBDEV_PMU    ] =  nv108_pmu_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c

@@ -26,7 +26,7 @@
 #include <nvif/class.h>
 
 #include <subdev/fb.h>
-#include <subdev/vm/nv04.h>
+#include <subdev/mmu/nv04.h>
 
 #include "priv.h"
 
@@ -62,8 +62,8 @@ nv04_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
 	}
 
 	if (priv->clone) {
-		struct nv04_vmmgr_priv *vmm = nv04_vmmgr(dmaobj);
-		struct nouveau_gpuobj *pgt = vmm->vm->pgt[0].obj[0];
+		struct nv04_mmu_priv *mmu = nv04_mmu(dmaobj);
+		struct nouveau_gpuobj *pgt = mmu->vm->pgt[0].obj[0];
 		if (!dmaobj->start)
 			return nouveau_gpuobj_dup(parent, pgt, pgpuobj);
 		offset  = nv_ro32(pgt, 8 + (offset >> 10));
@@ -88,7 +88,7 @@ nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 		 struct nouveau_object **pobject)
 {
 	struct nouveau_dmaeng *dmaeng = (void *)engine;
-	struct nv04_vmmgr_priv *vmm = nv04_vmmgr(engine);
+	struct nv04_mmu_priv *mmu = nv04_mmu(engine);
 	struct nv04_dmaobj_priv *priv;
 	int ret;
 
@@ -98,7 +98,7 @@ nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 		return ret;
 
 	if (priv->base.target == NV_MEM_TARGET_VM) {
-		if (nv_object(vmm)->oclass == &nv04_vmmgr_oclass)
+		if (nv_object(mmu)->oclass == &nv04_mmu_oclass)
 			priv->clone = true;
 		priv->base.target = NV_MEM_TARGET_PCI;
 		priv->base.access = NV_MEM_ACCESS_RW;

drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c

@@ -35,7 +35,7 @@
 #include <subdev/timer.h>
 #include <subdev/bar.h>
 #include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 
 #include <engine/dmaobj.h>
 #include <engine/fifo.h>

drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c

@@ -35,7 +35,7 @@
 #include <subdev/timer.h>
 #include <subdev/bar.h>
 #include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 
 #include <engine/dmaobj.h>
 

drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c

@@ -29,7 +29,7 @@
 #include <core/enum.h>
 
 #include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 #include <subdev/timer.h>
 
 #include <engine/fifo.h>

drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h

@@ -34,7 +34,7 @@
 #include <nvif/class.h>
 
 #include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 #include <subdev/bar.h>
 #include <subdev/timer.h>
 #include <subdev/mc.h>

drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c

@@ -25,7 +25,7 @@
 #include <core/os.h>
 #include <core/engctx.h>
 
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 #include <subdev/bar.h>
 #include <subdev/timer.h>
 

drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c

@@ -25,7 +25,7 @@
 #include <core/os.h>
 #include <core/engctx.h>
 
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 #include <subdev/bar.h>
 #include <subdev/timer.h>
 

drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild

@@ -15,5 +15,5 @@ include $(src)/nvkm/subdev/mxm/Kbuild
 include $(src)/nvkm/subdev/pmu/Kbuild
 include $(src)/nvkm/subdev/therm/Kbuild
 include $(src)/nvkm/subdev/timer/Kbuild
-include $(src)/nvkm/subdev/vm/Kbuild
+include $(src)/nvkm/subdev/mmu/Kbuild
 include $(src)/nvkm/subdev/volt/Kbuild

drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c

@@ -25,7 +25,7 @@
 #include <core/object.h>
 
 #include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 
 #include "priv.h"
 

drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c

@@ -26,7 +26,7 @@
 
 #include <subdev/timer.h>
 #include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 
 #include "priv.h"
 

drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c

@@ -26,7 +26,7 @@
 
 #include <subdev/timer.h>
 #include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 
 #include "priv.h"
 

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild

@@ -0,0 +1,6 @@
+nvkm-y += nvkm/subdev/mmu/base.o
+nvkm-y += nvkm/subdev/mmu/nv04.o
+nvkm-y += nvkm/subdev/mmu/nv41.o
+nvkm-y += nvkm/subdev/mmu/nv44.o
+nvkm-y += nvkm/subdev/mmu/nv50.o
+nvkm-y += nvkm/subdev/mmu/nvc0.o

drivers/gpu/drm/nouveau/nvkm/subdev/vm/base.c → drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c

@@ -26,20 +26,20 @@
 #include <core/mm.h>
 
 #include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 
 void
 nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node)
 {
 	struct nouveau_vm *vm = vma->vm;
-	struct nouveau_vmmgr *vmm = vm->vmm;
+	struct nouveau_mmu *mmu = vm->mmu;
 	struct nouveau_mm_node *r;
-	int big = vma->node->type != vmm->spg_shift;
+	int big = vma->node->type != mmu->spg_shift;
 	u32 offset = vma->node->offset + (delta >> 12);
 	u32 bits = vma->node->type - 12;
-	u32 pde  = (offset >> vmm->pgt_bits) - vm->fpde;
-	u32 pte  = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits;
-	u32 max  = 1 << (vmm->pgt_bits - bits);
+	u32 pde  = (offset >> mmu->pgt_bits) - vm->fpde;
+	u32 pte  = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits;
+	u32 max  = 1 << (mmu->pgt_bits - bits);
 	u32 end, len;
 
 	delta = 0;
@@ -55,7 +55,7 @@ nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node)
 				end = max;
 			len = end - pte;
 
-			vmm->map(vma, pgt, node, pte, len, phys, delta);
+			mmu->map(vma, pgt, node, pte, len, phys, delta);
 
 			num -= len;
 			pte += len;
@@ -69,7 +69,7 @@ nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node)
 		}
 	}
 
-	vmm->flush(vm);
+	mmu->flush(vm);
 }
 
 static void
@@ -77,14 +77,14 @@ nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length,
 			struct nouveau_mem *mem)
 {
 	struct nouveau_vm *vm = vma->vm;
-	struct nouveau_vmmgr *vmm = vm->vmm;
-	int big = vma->node->type != vmm->spg_shift;
+	struct nouveau_mmu *mmu = vm->mmu;
+	int big = vma->node->type != mmu->spg_shift;
 	u32 offset = vma->node->offset + (delta >> 12);
 	u32 bits = vma->node->type - 12;
 	u32 num  = length >> vma->node->type;
-	u32 pde  = (offset >> vmm->pgt_bits) - vm->fpde;
-	u32 pte  = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits;
-	u32 max  = 1 << (vmm->pgt_bits - bits);
+	u32 pde  = (offset >> mmu->pgt_bits) - vm->fpde;
+	u32 pte  = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits;
+	u32 max  = 1 << (mmu->pgt_bits - bits);
 	unsigned m, sglen;
 	u32 end, len;
 	int i;
@@ -102,7 +102,7 @@ nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length,
 		for (m = 0; m < len; m++) {
 			dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
 
-			vmm->map_sg(vma, pgt, mem, pte, 1, &addr);
+			mmu->map_sg(vma, pgt, mem, pte, 1, &addr);
 			num--;
 			pte++;
 
@@ -117,7 +117,7 @@ nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length,
 			for (; m < sglen; m++) {
 				dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
 
-				vmm->map_sg(vma, pgt, mem, pte, 1, &addr);
+				mmu->map_sg(vma, pgt, mem, pte, 1, &addr);
 				num--;
 				pte++;
 				if (num == 0)
@@ -127,7 +127,7 @@ nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length,
 
 	}
 finish:
-	vmm->flush(vm);
+	mmu->flush(vm);
 }
 
 static void
@@ -135,15 +135,15 @@ nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length,
 		  struct nouveau_mem *mem)
 {
 	struct nouveau_vm *vm = vma->vm;
-	struct nouveau_vmmgr *vmm = vm->vmm;
+	struct nouveau_mmu *mmu = vm->mmu;
 	dma_addr_t *list = mem->pages;
-	int big = vma->node->type != vmm->spg_shift;
+	int big = vma->node->type != mmu->spg_shift;
 	u32 offset = vma->node->offset + (delta >> 12);
 	u32 bits = vma->node->type - 12;
 	u32 num  = length >> vma->node->type;
-	u32 pde  = (offset >> vmm->pgt_bits) - vm->fpde;
-	u32 pte  = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits;
-	u32 max  = 1 << (vmm->pgt_bits - bits);
+	u32 pde  = (offset >> mmu->pgt_bits) - vm->fpde;
+	u32 pte  = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits;
+	u32 max  = 1 << (mmu->pgt_bits - bits);
 	u32 end, len;
 
 	while (num) {
@@ -154,7 +154,7 @@ nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length,
 			end = max;
 		len = end - pte;
 
-		vmm->map_sg(vma, pgt, mem, pte, len, list);
+		mmu->map_sg(vma, pgt, mem, pte, len, list);
 
 		num  -= len;
 		pte  += len;
@@ -165,7 +165,7 @@ nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length,
 		}
 	}
 
-	vmm->flush(vm);
+	mmu->flush(vm);
 }
 
 void
@@ -184,14 +184,14 @@ void
 nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length)
 {
 	struct nouveau_vm *vm = vma->vm;
-	struct nouveau_vmmgr *vmm = vm->vmm;
-	int big = vma->node->type != vmm->spg_shift;
+	struct nouveau_mmu *mmu = vm->mmu;
+	int big = vma->node->type != mmu->spg_shift;
 	u32 offset = vma->node->offset + (delta >> 12);
 	u32 bits = vma->node->type - 12;
 	u32 num  = length >> vma->node->type;
-	u32 pde  = (offset >> vmm->pgt_bits) - vm->fpde;
-	u32 pte  = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits;
-	u32 max  = 1 << (vmm->pgt_bits - bits);
+	u32 pde  = (offset >> mmu->pgt_bits) - vm->fpde;
+	u32 pte  = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits;
+	u32 max  = 1 << (mmu->pgt_bits - bits);
 	u32 end, len;
 
 	while (num) {
@@ -202,7 +202,7 @@ nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length)
 			end = max;
 		len = end - pte;
 
-		vmm->unmap(pgt, pte, len);
+		mmu->unmap(pgt, pte, len);
 
 		num -= len;
 		pte += len;
@@ -212,7 +212,7 @@ nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length)
 		}
 	}
 
-	vmm->flush(vm);
+	mmu->flush(vm);
 }
 
 void
@@ -224,7 +224,7 @@ nouveau_vm_unmap(struct nouveau_vma *vma)
 static void
 nouveau_vm_unmap_pgt(struct nouveau_vm *vm, int big, u32 fpde, u32 lpde)
 {
-	struct nouveau_vmmgr *vmm = vm->vmm;
+	struct nouveau_mmu *mmu = vm->mmu;
 	struct nouveau_vm_pgd *vpgd;
 	struct nouveau_vm_pgt *vpgt;
 	struct nouveau_gpuobj *pgt;
@@ -239,47 +239,47 @@ nouveau_vm_unmap_pgt(struct nouveau_vm *vm, int big, u32 fpde, u32 lpde)
 		vpgt->obj[big] = NULL;
 
 		list_for_each_entry(vpgd, &vm->pgd_list, head) {
-			vmm->map_pgt(vpgd->obj, pde, vpgt->obj);
+			mmu->map_pgt(vpgd->obj, pde, vpgt->obj);
 		}
 
-		mutex_unlock(&nv_subdev(vmm)->mutex);
+		mutex_unlock(&nv_subdev(mmu)->mutex);
 		nouveau_gpuobj_ref(NULL, &pgt);
-		mutex_lock(&nv_subdev(vmm)->mutex);
+		mutex_lock(&nv_subdev(mmu)->mutex);
 	}
 }
 
 static int
 nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type)
 {
-	struct nouveau_vmmgr *vmm = vm->vmm;
+	struct nouveau_mmu *mmu = vm->mmu;
 	struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde];
 	struct nouveau_vm_pgd *vpgd;
 	struct nouveau_gpuobj *pgt;
-	int big = (type != vmm->spg_shift);
+	int big = (type != mmu->spg_shift);
 	u32 pgt_size;
 	int ret;
 
-	pgt_size  = (1 << (vmm->pgt_bits + 12)) >> type;
+	pgt_size  = (1 << (mmu->pgt_bits + 12)) >> type;
 	pgt_size *= 8;
 
-	mutex_unlock(&nv_subdev(vmm)->mutex);
-	ret = nouveau_gpuobj_new(nv_object(vm->vmm), NULL, pgt_size, 0x1000,
+	mutex_unlock(&nv_subdev(mmu)->mutex);
+	ret = nouveau_gpuobj_new(nv_object(vm->mmu), NULL, pgt_size, 0x1000,
 				 NVOBJ_FLAG_ZERO_ALLOC, &pgt);
-	mutex_lock(&nv_subdev(vmm)->mutex);
+	mutex_lock(&nv_subdev(mmu)->mutex);
 	if (unlikely(ret))
 		return ret;
 
 	/* someone beat us to filling the PDE while we didn't have the lock */
 	if (unlikely(vpgt->refcount[big]++)) {
-		mutex_unlock(&nv_subdev(vmm)->mutex);
+		mutex_unlock(&nv_subdev(mmu)->mutex);
 		nouveau_gpuobj_ref(NULL, &pgt);
-		mutex_lock(&nv_subdev(vmm)->mutex);
+		mutex_lock(&nv_subdev(mmu)->mutex);
 		return 0;
 	}
 
 	vpgt->obj[big] = pgt;
 	list_for_each_entry(vpgd, &vm->pgd_list, head) {
-		vmm->map_pgt(vpgd->obj, pde, vpgt->obj);
+		mmu->map_pgt(vpgd->obj, pde, vpgt->obj);
 	}
 
 	return 0;
@@ -289,26 +289,26 @@ int
 nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift,
 	       u32 access, struct nouveau_vma *vma)
 {
-	struct nouveau_vmmgr *vmm = vm->vmm;
+	struct nouveau_mmu *mmu = vm->mmu;
 	u32 align = (1 << page_shift) >> 12;
 	u32 msize = size >> 12;
 	u32 fpde, lpde, pde;
 	int ret;
 
-	mutex_lock(&nv_subdev(vmm)->mutex);
+	mutex_lock(&nv_subdev(mmu)->mutex);
 	ret = nouveau_mm_head(&vm->mm, 0, page_shift, msize, msize, align,
 			     &vma->node);
 	if (unlikely(ret != 0)) {
-		mutex_unlock(&nv_subdev(vmm)->mutex);
+		mutex_unlock(&nv_subdev(mmu)->mutex);
 		return ret;
 	}
 
-	fpde = (vma->node->offset >> vmm->pgt_bits);
-	lpde = (vma->node->offset + vma->node->length - 1) >> vmm->pgt_bits;
+	fpde = (vma->node->offset >> mmu->pgt_bits);
+	lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits;
 
 	for (pde = fpde; pde <= lpde; pde++) {
 		struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde];
-		int big = (vma->node->type != vmm->spg_shift);
+		int big = (vma->node->type != mmu->spg_shift);
 
 		if (likely(vpgt->refcount[big])) {
 			vpgt->refcount[big]++;
@@ -320,11 +320,11 @@ nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift,
 			if (pde != fpde)
 				nouveau_vm_unmap_pgt(vm, big, fpde, pde - 1);
 			nouveau_mm_free(&vm->mm, &vma->node);
-			mutex_unlock(&nv_subdev(vmm)->mutex);
+			mutex_unlock(&nv_subdev(mmu)->mutex);
 			return ret;
 		}
 	}
-	mutex_unlock(&nv_subdev(vmm)->mutex);
+	mutex_unlock(&nv_subdev(mmu)->mutex);
 
 	vma->vm = NULL;
 	nouveau_vm_ref(vm, &vma->vm, NULL);
@@ -337,24 +337,24 @@ void
 nouveau_vm_put(struct nouveau_vma *vma)
 {
 	struct nouveau_vm *vm = vma->vm;
-	struct nouveau_vmmgr *vmm = vm->vmm;
+	struct nouveau_mmu *mmu = vm->mmu;
 	u32 fpde, lpde;
 
 	if (unlikely(vma->node == NULL))
 		return;
-	fpde = (vma->node->offset >> vmm->pgt_bits);
-	lpde = (vma->node->offset + vma->node->length - 1) >> vmm->pgt_bits;
+	fpde = (vma->node->offset >> mmu->pgt_bits);
+	lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits;
 
-	mutex_lock(&nv_subdev(vmm)->mutex);
-	nouveau_vm_unmap_pgt(vm, vma->node->type != vmm->spg_shift, fpde, lpde);
+	mutex_lock(&nv_subdev(mmu)->mutex);
+	nouveau_vm_unmap_pgt(vm, vma->node->type != mmu->spg_shift, fpde, lpde);
 	nouveau_mm_free(&vm->mm, &vma->node);
-	mutex_unlock(&nv_subdev(vmm)->mutex);
+	mutex_unlock(&nv_subdev(mmu)->mutex);
 
 	nouveau_vm_ref(NULL, &vma->vm, NULL);
 }
 
 int
-nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length,
+nouveau_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length,
 		  u64 mm_offset, u32 block, struct nouveau_vm **pvm)
 {
 	struct nouveau_vm *vm;
@@ -366,10 +366,10 @@ nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length,
 		return -ENOMEM;
 
 	INIT_LIST_HEAD(&vm->pgd_list);
-	vm->vmm = vmm;
+	vm->mmu = mmu;
 	kref_init(&vm->refcount);
-	vm->fpde = offset >> (vmm->pgt_bits + 12);
-	vm->lpde = (offset + length - 1) >> (vmm->pgt_bits + 12);
+	vm->fpde = offset >> (mmu->pgt_bits + 12);
+	vm->lpde = (offset + length - 1) >> (mmu->pgt_bits + 12);
 
 	vm->pgt  = vzalloc((vm->lpde - vm->fpde + 1) * sizeof(*vm->pgt));
 	if (!vm->pgt) {
@@ -394,14 +394,14 @@ int
 nouveau_vm_new(struct nouveau_device *device, u64 offset, u64 length,
 	       u64 mm_offset, struct nouveau_vm **pvm)
 {
-	struct nouveau_vmmgr *vmm = nouveau_vmmgr(device);
-	return vmm->create(vmm, offset, length, mm_offset, pvm);
+	struct nouveau_mmu *mmu = nouveau_mmu(device);
+	return mmu->create(mmu, offset, length, mm_offset, pvm);
 }
 
 static int
 nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd)
 {
-	struct nouveau_vmmgr *vmm = vm->vmm;
+	struct nouveau_mmu *mmu = vm->mmu;
 	struct nouveau_vm_pgd *vpgd;
 	int i;
 
@@ -414,25 +414,25 @@ nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd)
 
 	nouveau_gpuobj_ref(pgd, &vpgd->obj);
 
-	mutex_lock(&nv_subdev(vmm)->mutex);
+	mutex_lock(&nv_subdev(mmu)->mutex);
 	for (i = vm->fpde; i <= vm->lpde; i++)
-		vmm->map_pgt(pgd, i, vm->pgt[i - vm->fpde].obj);
+		mmu->map_pgt(pgd, i, vm->pgt[i - vm->fpde].obj);
 	list_add(&vpgd->head, &vm->pgd_list);
-	mutex_unlock(&nv_subdev(vmm)->mutex);
+	mutex_unlock(&nv_subdev(mmu)->mutex);
 	return 0;
 }
 
 static void
 nouveau_vm_unlink(struct nouveau_vm *vm, struct nouveau_gpuobj *mpgd)
 {
-	struct nouveau_vmmgr *vmm = vm->vmm;
+	struct nouveau_mmu *mmu = vm->mmu;
 	struct nouveau_vm_pgd *vpgd, *tmp;
 	struct nouveau_gpuobj *pgd = NULL;
 
 	if (!mpgd)
 		return;
 
-	mutex_lock(&nv_subdev(vmm)->mutex);
+	mutex_lock(&nv_subdev(mmu)->mutex);
 	list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) {
 		if (vpgd->obj == mpgd) {
 			pgd = vpgd->obj;
@@ -441,7 +441,7 @@ nouveau_vm_unlink(struct nouveau_vm *vm, struct nouveau_gpuobj *mpgd)
 			break;
 		}
 	}
-	mutex_unlock(&nv_subdev(vmm)->mutex);
+	mutex_unlock(&nv_subdev(mmu)->mutex);
 
 	nouveau_gpuobj_ref(NULL, &pgd);
 }

drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.c → drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c

@@ -70,26 +70,26 @@ nv04_vm_flush(struct nouveau_vm *vm)
  ******************************************************************************/
 
 int
-nv04_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, u64 mmstart,
+nv04_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, u64 mmstart,
 	       struct nouveau_vm **pvm)
 {
 	return -EINVAL;
 }
 
 /*******************************************************************************
- * VMMGR subdev
+ * MMU subdev
  ******************************************************************************/
 
 static int
-nv04_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv04_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 		struct nouveau_oclass *oclass, void *data, u32 size,
 		struct nouveau_object **pobject)
 {
-	struct nv04_vmmgr_priv *priv;
+	struct nv04_mmu_priv *priv;
 	struct nouveau_gpuobj *dma;
 	int ret;
 
-	ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIGART",
+	ret = nouveau_mmu_create(parent, engine, oclass, "PCIGART",
 				   "pcigart", &priv);
 	*pobject = nv_object(priv);
 	if (ret)
@@ -125,9 +125,9 @@ nv04_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 }
 
 void
-nv04_vmmgr_dtor(struct nouveau_object *object)
+nv04_mmu_dtor(struct nouveau_object *object)
 {
-	struct nv04_vmmgr_priv *priv = (void *)object;
+	struct nv04_mmu_priv *priv = (void *)object;
 	if (priv->vm) {
 		nouveau_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]);
 		nouveau_vm_ref(NULL, &priv->vm, NULL);
@@ -136,16 +136,16 @@ nv04_vmmgr_dtor(struct nouveau_object *object)
 		pci_free_consistent(nv_device(priv)->pdev, 16 * 1024,
 				    priv->nullp, priv->null);
 	}
-	nouveau_vmmgr_destroy(&priv->base);
+	nouveau_mmu_destroy(&priv->base);
 }
 
 struct nouveau_oclass
-nv04_vmmgr_oclass = {
-	.handle = NV_SUBDEV(VM, 0x04),
+nv04_mmu_oclass = {
+	.handle = NV_SUBDEV(MMU, 0x04),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_vmmgr_ctor,
-		.dtor = nv04_vmmgr_dtor,
-		.init = _nouveau_vmmgr_init,
-		.fini = _nouveau_vmmgr_fini,
+		.ctor = nv04_mmu_ctor,
+		.dtor = nv04_mmu_dtor,
+		.init = _nouveau_mmu_init,
+		.fini = _nouveau_mmu_fini,
 	},
 };

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h

@@ -0,0 +1,19 @@
+#ifndef __NV04_MMU_PRIV__
+#define __NV04_MMU_PRIV__
+
+#include <subdev/mmu.h>
+
+struct nv04_mmu_priv {
+	struct nouveau_mmu base;
+	struct nouveau_vm *vm;
+	dma_addr_t null;
+	void *nullp;
+};
+
+static inline struct nv04_mmu_priv *
+nv04_mmu(void *obj)
+{
+	return (void *)nouveau_mmu(obj);
+}
+
+#endif

drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv41.c → drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c

@@ -26,7 +26,7 @@
 #include <core/option.h>
 
 #include <subdev/timer.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 
 #include "nv04.h"
 
@@ -67,7 +67,7 @@ nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
 static void
 nv41_vm_flush(struct nouveau_vm *vm)
 {
-	struct nv04_vmmgr_priv *priv = (void *)vm->vmm;
+	struct nv04_mmu_priv *priv = (void *)vm->mmu;
 
 	mutex_lock(&nv_subdev(priv)->mutex);
 	nv_wr32(priv, 0x100810, 0x00000022);
@@ -80,25 +80,25 @@ nv41_vm_flush(struct nouveau_vm *vm)
 }
 
 /*******************************************************************************
- * VMMGR subdev
+ * MMU subdev
  ******************************************************************************/
 
 static int
-nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv41_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 		struct nouveau_oclass *oclass, void *data, u32 size,
 		struct nouveau_object **pobject)
 {
 	struct nouveau_device *device = nv_device(parent);
-	struct nv04_vmmgr_priv *priv;
+	struct nv04_mmu_priv *priv;
 	int ret;
 
 	if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
 	    !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) {
-		return nouveau_object_ctor(parent, engine, &nv04_vmmgr_oclass,
+		return nouveau_object_ctor(parent, engine, &nv04_mmu_oclass,
 					   data, size, pobject);
 	}
 
-	ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIEGART",
+	ret = nouveau_mmu_create(parent, engine, oclass, "PCIEGART",
 				   "pciegart", &priv);
 	*pobject = nv_object(priv);
 	if (ret)
@@ -131,13 +131,13 @@ nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 }
 
 static int
-nv41_vmmgr_init(struct nouveau_object *object)
+nv41_mmu_init(struct nouveau_object *object)
 {
-	struct nv04_vmmgr_priv *priv = (void *)object;
+	struct nv04_mmu_priv *priv = (void *)object;
 	struct nouveau_gpuobj *dma = priv->vm->pgt[0].obj[0];
 	int ret;
 
-	ret = nouveau_vmmgr_init(&priv->base);
+	ret = nouveau_mmu_init(&priv->base);
 	if (ret)
 		return ret;
 
@@ -148,12 +148,12 @@ nv41_vmmgr_init(struct nouveau_object *object)
 }
 
 struct nouveau_oclass
-nv41_vmmgr_oclass = {
-	.handle = NV_SUBDEV(VM, 0x41),
+nv41_mmu_oclass = {
+	.handle = NV_SUBDEV(MMU, 0x41),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv41_vmmgr_ctor,
-		.dtor = nv04_vmmgr_dtor,
-		.init = nv41_vmmgr_init,
-		.fini = _nouveau_vmmgr_fini,
+		.ctor = nv41_mmu_ctor,
+		.dtor = nv04_mmu_dtor,
+		.init = nv41_mmu_init,
+		.fini = _nouveau_mmu_fini,
 	},
 };

drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv44.c → drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c

@@ -26,7 +26,7 @@
 #include <core/option.h>
 
 #include <subdev/timer.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 
 #include "nv04.h"
 
@@ -87,7 +87,7 @@ static void
 nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
 	       struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
 {
-	struct nv04_vmmgr_priv *priv = (void *)vma->vm->vmm;
+	struct nv04_mmu_priv *priv = (void *)vma->vm->mmu;
 	u32 tmp[4];
 	int i;
 
@@ -117,7 +117,7 @@ nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
 static void
 nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
 {
-	struct nv04_vmmgr_priv *priv = (void *)nouveau_vmmgr(pgt);
+	struct nv04_mmu_priv *priv = (void *)nouveau_mmu(pgt);
 
 	if (pte & 3) {
 		u32  max = 4 - (pte & 3);
@@ -142,7 +142,7 @@ nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
 static void
 nv44_vm_flush(struct nouveau_vm *vm)
 {
-	struct nv04_vmmgr_priv *priv = (void *)vm->vmm;
+	struct nv04_mmu_priv *priv = (void *)vm->mmu;
 	nv_wr32(priv, 0x100814, priv->base.limit - NV44_GART_PAGE);
 	nv_wr32(priv, 0x100808, 0x00000020);
 	if (!nv_wait(priv, 0x100808, 0x00000001, 0x00000001))
@@ -151,25 +151,25 @@ nv44_vm_flush(struct nouveau_vm *vm)
 }
 
 /*******************************************************************************
- * VMMGR subdev
+ * MMU subdev
  ******************************************************************************/
 
 static int
-nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv44_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 		struct nouveau_oclass *oclass, void *data, u32 size,
 		struct nouveau_object **pobject)
 {
 	struct nouveau_device *device = nv_device(parent);
-	struct nv04_vmmgr_priv *priv;
+	struct nv04_mmu_priv *priv;
 	int ret;
 
 	if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
 	    !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) {
-		return nouveau_object_ctor(parent, engine, &nv04_vmmgr_oclass,
+		return nouveau_object_ctor(parent, engine, &nv04_mmu_oclass,
 					   data, size, pobject);
 	}
 
-	ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIEGART",
+	ret = nouveau_mmu_create(parent, engine, oclass, "PCIEGART",
 				   "pciegart", &priv);
 	*pobject = nv_object(priv);
 	if (ret)
@@ -208,14 +208,14 @@ nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 }
 
 static int
-nv44_vmmgr_init(struct nouveau_object *object)
+nv44_mmu_init(struct nouveau_object *object)
 {
-	struct nv04_vmmgr_priv *priv = (void *)object;
+	struct nv04_mmu_priv *priv = (void *)object;
 	struct nouveau_gpuobj *gart = priv->vm->pgt[0].obj[0];
 	u32 addr;
 	int ret;
 
-	ret = nouveau_vmmgr_init(&priv->base);
+	ret = nouveau_mmu_init(&priv->base);
 	if (ret)
 		return ret;
 
@@ -238,12 +238,12 @@ nv44_vmmgr_init(struct nouveau_object *object)
 }
 
 struct nouveau_oclass
-nv44_vmmgr_oclass = {
-	.handle = NV_SUBDEV(VM, 0x44),
+nv44_mmu_oclass = {
+	.handle = NV_SUBDEV(MMU, 0x44),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv44_vmmgr_ctor,
-		.dtor = nv04_vmmgr_dtor,
-		.init = nv44_vmmgr_init,
-		.fini = _nouveau_vmmgr_fini,
+		.ctor = nv44_mmu_ctor,
+		.dtor = nv04_mmu_dtor,
+		.init = nv44_mmu_init,
+		.fini = _nouveau_mmu_fini,
 	},
 };

drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv50.c → drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c

@@ -28,10 +28,10 @@
 #include <subdev/timer.h>
 #include <subdev/fb.h>
 #include <subdev/bar.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 
-struct nv50_vmmgr_priv {
-	struct nouveau_vmmgr base;
+struct nv50_mmu_priv {
+	struct nouveau_mmu base;
 };
 
 static void
@@ -86,8 +86,8 @@ nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
 
 	/* IGPs don't have real VRAM, re-target to stolen system memory */
 	target = 0;
-	if (nouveau_fb(vma->vm->vmm)->ram->stolen) {
-		phys += nouveau_fb(vma->vm->vmm)->ram->stolen;
+	if (nouveau_fb(vma->vm->mmu)->ram->stolen) {
+		phys += nouveau_fb(vma->vm->mmu)->ram->stolen;
 		target = 3;
 	}
 
@@ -151,7 +151,7 @@ nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
 static void
 nv50_vm_flush(struct nouveau_vm *vm)
 {
-	struct nv50_vmmgr_priv *priv = (void *)vm->vmm;
+	struct nv50_mmu_priv *priv = (void *)vm->mmu;
 	struct nouveau_bar *bar = nouveau_bar(priv);
 	struct nouveau_engine *engine;
 	int i, vme;
@@ -191,25 +191,25 @@ nv50_vm_flush(struct nouveau_vm *vm)
 }
 
 static int
-nv50_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length,
+nv50_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length,
 	       u64 mm_offset, struct nouveau_vm **pvm)
 {
-	u32 block = (1 << (vmm->pgt_bits + 12));
+	u32 block = (1 << (mmu->pgt_bits + 12));
 	if (block > length)
 		block = length;
 
-	return nouveau_vm_create(vmm, offset, length, mm_offset, block, pvm);
+	return nouveau_vm_create(mmu, offset, length, mm_offset, block, pvm);
 }
 
 static int
-nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv50_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 		struct nouveau_oclass *oclass, void *data, u32 size,
 		struct nouveau_object **pobject)
 {
-	struct nv50_vmmgr_priv *priv;
+	struct nv50_mmu_priv *priv;
 	int ret;
 
-	ret = nouveau_vmmgr_create(parent, engine, oclass, "VM", "vm", &priv);
+	ret = nouveau_mmu_create(parent, engine, oclass, "VM", "vm", &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
@@ -229,12 +229,12 @@ nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 }
 
 struct nouveau_oclass
-nv50_vmmgr_oclass = {
-	.handle = NV_SUBDEV(VM, 0x50),
+nv50_mmu_oclass = {
+	.handle = NV_SUBDEV(MMU, 0x50),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_vmmgr_ctor,
-		.dtor = _nouveau_vmmgr_dtor,
-		.init = _nouveau_vmmgr_init,
-		.fini = _nouveau_vmmgr_fini,
+		.ctor = nv50_mmu_ctor,
+		.dtor = _nouveau_mmu_dtor,
+		.init = _nouveau_mmu_init,
+		.fini = _nouveau_mmu_fini,
 	},
 };

drivers/gpu/drm/nouveau/nvkm/subdev/vm/nvc0.c → drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c

@@ -27,12 +27,12 @@
 
 #include <subdev/timer.h>
 #include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
 #include <subdev/ltc.h>
 #include <subdev/bar.h>
 
-struct nvc0_vmmgr_priv {
-	struct nouveau_vmmgr base;
+struct nvc0_mmu_priv {
+	struct nouveau_mmu base;
 };
 
 
@@ -116,7 +116,7 @@ nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
 	pte <<= 3;
 
 	if (mem->tag) {
-		struct nouveau_ltc *ltc = nouveau_ltc(vma->vm->vmm);
+		struct nouveau_ltc *ltc = nouveau_ltc(vma->vm->mmu);
 		u32 tag = mem->tag->offset + (delta >> 17);
 		phys |= (u64)tag << (32 + 12);
 		next |= (u64)1   << (32 + 12);
@@ -162,7 +162,7 @@ nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
 static void
 nvc0_vm_flush(struct nouveau_vm *vm)
 {
-	struct nvc0_vmmgr_priv *priv = (void *)vm->vmm;
+	struct nvc0_mmu_priv *priv = (void *)vm->mmu;
 	struct nouveau_bar *bar = nouveau_bar(priv);
 	struct nouveau_vm_pgd *vpgd;
 	u32 type;
@@ -196,21 +196,21 @@ nvc0_vm_flush(struct nouveau_vm *vm)
 }
 
 static int
-nvc0_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length,
+nvc0_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length,
 	       u64 mm_offset, struct nouveau_vm **pvm)
 {
-	return nouveau_vm_create(vmm, offset, length, mm_offset, 4096, pvm);
+	return nouveau_vm_create(mmu, offset, length, mm_offset, 4096, pvm);
 }
 
 static int
-nvc0_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nvc0_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 		struct nouveau_oclass *oclass, void *data, u32 size,
 		struct nouveau_object **pobject)
 {
-	struct nvc0_vmmgr_priv *priv;
+	struct nvc0_mmu_priv *priv;
 	int ret;
 
-	ret = nouveau_vmmgr_create(parent, engine, oclass, "VM", "vm", &priv);
+	ret = nouveau_mmu_create(parent, engine, oclass, "VM", "vm", &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
@@ -230,12 +230,12 @@ nvc0_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 }
 
 struct nouveau_oclass
-nvc0_vmmgr_oclass = {
-	.handle = NV_SUBDEV(VM, 0xc0),
+nvc0_mmu_oclass = {
+	.handle = NV_SUBDEV(MMU, 0xc0),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_vmmgr_ctor,
-		.dtor = _nouveau_vmmgr_dtor,
-		.init = _nouveau_vmmgr_init,
-		.fini = _nouveau_vmmgr_fini,
+		.ctor = nvc0_mmu_ctor,
+		.dtor = _nouveau_mmu_dtor,
+		.init = _nouveau_mmu_init,
+		.fini = _nouveau_mmu_fini,
 	},
 };

drivers/gpu/drm/nouveau/nvkm/subdev/vm/Kbuild

@@ -1,6 +0,0 @@
-nvkm-y += nvkm/subdev/vm/base.o
-nvkm-y += nvkm/subdev/vm/nv04.o
-nvkm-y += nvkm/subdev/vm/nv41.o
-nvkm-y += nvkm/subdev/vm/nv44.o
-nvkm-y += nvkm/subdev/vm/nv50.o
-nvkm-y += nvkm/subdev/vm/nvc0.o

drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.h

@@ -1,19 +0,0 @@
-#ifndef __NV04_VMMGR_PRIV__
-#define __NV04_VMMGR_PRIV__
-
-#include <subdev/vm.h>
-
-struct nv04_vmmgr_priv {
-	struct nouveau_vmmgr base;
-	struct nouveau_vm *vm;
-	dma_addr_t null;
-	void *nullp;
-};
-
-static inline struct nv04_vmmgr_priv *
-nv04_vmmgr(void *obj)
-{
-	return (void *)nouveau_vmmgr(obj);
-}
-
-#endif