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@@ -366,21 +366,24 @@ static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
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void *p_data, unsigned int bytes)
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{
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- *(u32 *)p_data = (1 << 17);
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- return 0;
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-}
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-
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-static int dpy_reg_mmio_read_2(struct intel_vgpu *vgpu, unsigned int offset,
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- void *p_data, unsigned int bytes)
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-{
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- *(u32 *)p_data = 3;
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- return 0;
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-}
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+ switch (offset) {
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+ case 0xe651c:
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+ case 0xe661c:
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+ case 0xe671c:
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+ case 0xe681c:
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+ vgpu_vreg(vgpu, offset) = 1 << 17;
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+ break;
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+ case 0xe6c04:
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+ vgpu_vreg(vgpu, offset) = 0x3;
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+ break;
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+ case 0xe6e1c:
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+ vgpu_vreg(vgpu, offset) = 0x2f << 16;
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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-static int dpy_reg_mmio_read_3(struct intel_vgpu *vgpu, unsigned int offset,
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- void *p_data, unsigned int bytes)
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-{
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- *(u32 *)p_data = (0x2f << 16);
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+ read_vreg(vgpu, offset, p_data, bytes);
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return 0;
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}
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@@ -1991,8 +1994,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
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MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL);
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MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL);
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MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL);
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- MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read_2, NULL);
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- MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read_3, NULL);
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+ MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read, NULL);
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+ MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read, NULL);
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MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
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PORTA_HOTPLUG_STATUS_MASK
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