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@@ -25,6 +25,80 @@
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#include <core/pci.h>
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+static int
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+g84_pcie_version_supported(struct nvkm_pci *pci)
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+{
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+ /* g84 and g86 report wrong information about what they support */
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+ return 1;
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+}
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+
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+int
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+g84_pcie_version(struct nvkm_pci *pci)
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+{
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+ struct nvkm_device *device = pci->subdev.device;
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+ return (nvkm_rd32(device, 0x00154c) & 0x1) + 1;
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+}
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+
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+void
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+g84_pcie_set_version(struct nvkm_pci *pci, u8 ver)
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+{
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+ struct nvkm_device *device = pci->subdev.device;
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+ nvkm_mask(device, 0x00154c, 0x1, (ver >= 2 ? 0x1 : 0x0));
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+}
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+
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+static void
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+g84_pcie_set_cap_speed(struct nvkm_pci *pci, bool full_speed)
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+{
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+ struct nvkm_device *device = pci->subdev.device;
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+ nvkm_mask(device, 0x00154c, 0x80, full_speed ? 0x80 : 0x0);
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+}
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+
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+enum nvkm_pcie_speed
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+g84_pcie_cur_speed(struct nvkm_pci *pci)
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+{
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+ u32 reg_v = nvkm_pci_rd32(pci, 0x88) & 0x30000;
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+ switch (reg_v) {
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+ case 0x30000:
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+ return NVKM_PCIE_SPEED_8_0;
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+ case 0x20000:
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+ return NVKM_PCIE_SPEED_5_0;
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+ case 0x10000:
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+ default:
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+ return NVKM_PCIE_SPEED_2_5;
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+ }
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+}
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+
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+enum nvkm_pcie_speed
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+g84_pcie_max_speed(struct nvkm_pci *pci)
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+{
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+ u32 reg_v = nvkm_pci_rd32(pci, 0x460) & 0x3300;
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+ if (reg_v == 0x2200)
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+ return NVKM_PCIE_SPEED_5_0;
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+ return NVKM_PCIE_SPEED_2_5;
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+}
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+
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+void
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+g84_pcie_set_link_speed(struct nvkm_pci *pci, enum nvkm_pcie_speed speed)
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+{
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+ u32 mask_value;
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+
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+ if (speed == NVKM_PCIE_SPEED_5_0)
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+ mask_value = 0x20;
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+ else
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+ mask_value = 0x10;
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+
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+ nvkm_pci_mask(pci, 0x460, 0x30, mask_value);
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+ nvkm_pci_mask(pci, 0x460, 0x1, 0x1);
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+}
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+
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+int
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+g84_pcie_set_link(struct nvkm_pci *pci, enum nvkm_pcie_speed speed, u8 width)
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+{
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+ g84_pcie_set_cap_speed(pci, speed == NVKM_PCIE_SPEED_5_0);
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+ g84_pcie_set_link_speed(pci, speed);
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+ return 0;
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+}
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+
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void
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g84_pci_init(struct nvkm_pci *pci)
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{
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@@ -48,6 +122,14 @@ g84_pci_init(struct nvkm_pci *pci)
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nvkm_pci_mask(pci, 0x041c, 0x00000060, 0x00000000);
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}
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+int
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+g84_pcie_init(struct nvkm_pci *pci)
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+{
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+ bool full_speed = g84_pcie_cur_speed(pci) == NVKM_PCIE_SPEED_5_0;
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+ g84_pcie_set_cap_speed(pci, full_speed);
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+ return 0;
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+}
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+
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static const struct nvkm_pci_func
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g84_pci_func = {
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.init = g84_pci_init,
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@@ -55,6 +137,16 @@ g84_pci_func = {
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.wr08 = nv40_pci_wr08,
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.wr32 = nv40_pci_wr32,
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.msi_rearm = nv46_pci_msi_rearm,
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+
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+ .pcie.init = g84_pcie_init,
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+ .pcie.set_link = g84_pcie_set_link,
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+
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+ .pcie.max_speed = g84_pcie_max_speed,
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+ .pcie.cur_speed = g84_pcie_cur_speed,
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+
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+ .pcie.set_version = g84_pcie_set_version,
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+ .pcie.version = g84_pcie_version,
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+ .pcie.version_supported = g84_pcie_version_supported,
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};
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int
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