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@@ -707,6 +707,14 @@
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#define PM_CTRL1 0xFF44
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#define PM_CTRL1 0xFF44
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#define PM_CTRL2 0xFF45
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#define PM_CTRL2 0xFF45
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#define PM_CTRL3 0xFF46
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#define PM_CTRL3 0xFF46
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+#define SDIO_SEND_PME_EN 0x80
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+#define FORCE_RC_MODE_ON 0x40
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+#define FORCE_RX50_LINK_ON 0x20
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+#define D3_DELINK_MODE_EN 0x10
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+#define USE_PESRTB_CTL_DELINK 0x08
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+#define DELAY_PIN_WAKE 0x04
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+#define RESET_PIN_WAKE 0x02
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+#define PM_WAKE_EN 0x01
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#define PM_CTRL4 0xFF47
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#define PM_CTRL4 0xFF47
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/* Memory mapping */
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/* Memory mapping */
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@@ -752,6 +760,14 @@
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#define PHY_DUM_REG 0x1F
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#define PHY_DUM_REG 0x1F
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#define LCTLR 0x80
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#define LCTLR 0x80
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+#define LCTLR_EXT_SYNC 0x80
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+#define LCTLR_COMMON_CLOCK_CFG 0x40
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+#define LCTLR_RETRAIN_LINK 0x20
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+#define LCTLR_LINK_DISABLE 0x10
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+#define LCTLR_RCB 0x08
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+#define LCTLR_RESERVED 0x04
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+#define LCTLR_ASPM_CTL_MASK 0x03
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+
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#define PCR_SETTING_REG1 0x724
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#define PCR_SETTING_REG1 0x724
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#define PCR_SETTING_REG2 0x814
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#define PCR_SETTING_REG2 0x814
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#define PCR_SETTING_REG3 0x747
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#define PCR_SETTING_REG3 0x747
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@@ -967,4 +983,16 @@ static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)
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return (u8 *)(pcr->host_cmds_ptr);
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return (u8 *)(pcr->host_cmds_ptr);
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}
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}
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+static inline int rtsx_pci_update_cfg_byte(struct rtsx_pcr *pcr, int addr,
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+ u8 mask, u8 append)
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+{
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+ int err;
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+ u8 val;
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+
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+ err = pci_read_config_byte(pcr->pci, addr, &val);
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+ if (err < 0)
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+ return err;
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+ return pci_write_config_byte(pcr->pci, addr, (val & mask) | append);
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+}
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+
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#endif
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#endif
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