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@@ -249,6 +249,29 @@ static int lan9303_read(struct regmap *regmap, unsigned int offset, u32 *reg)
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return -EIO;
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}
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+/* Wait a while until mask & reg == value. Otherwise return timeout. */
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+static int lan9303_read_wait(struct lan9303 *chip, int offset, u32 mask)
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+{
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+ int i;
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+
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+ for (i = 0; i < 25; i++) {
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+ u32 reg;
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+ int ret;
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+
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+ ret = lan9303_read(chip->regmap, offset, ®);
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+ if (ret) {
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+ dev_err(chip->dev, "%s failed to read offset %d: %d\n",
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+ __func__, offset, ret);
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+ return ret;
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+ }
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+ if (!(reg & mask))
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+ return 0;
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+ usleep_range(1000, 2000);
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+ }
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+
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+ return -ETIMEDOUT;
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+}
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+
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static int lan9303_virt_phy_reg_read(struct lan9303 *chip, int regnum)
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{
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int ret;
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@@ -274,22 +297,8 @@ static int lan9303_virt_phy_reg_write(struct lan9303 *chip, int regnum, u16 val)
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static int lan9303_indirect_phy_wait_for_completion(struct lan9303 *chip)
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{
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- int ret, i;
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- u32 reg;
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-
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- for (i = 0; i < 25; i++) {
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- ret = lan9303_read(chip->regmap, LAN9303_PMI_ACCESS, ®);
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- if (ret) {
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- dev_err(chip->dev,
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- "Failed to read pmi access status: %d\n", ret);
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- return ret;
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- }
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- if (!(reg & LAN9303_PMI_ACCESS_MII_BUSY))
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- return 0;
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- usleep_range(1000, 2000);
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- }
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-
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- return -EIO;
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+ return lan9303_read_wait(chip, LAN9303_PMI_ACCESS,
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+ LAN9303_PMI_ACCESS_MII_BUSY);
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}
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static int lan9303_indirect_phy_read(struct lan9303 *chip, int addr, int regnum)
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@@ -366,22 +375,8 @@ EXPORT_SYMBOL_GPL(lan9303_indirect_phy_ops);
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static int lan9303_switch_wait_for_completion(struct lan9303 *chip)
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{
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- int ret, i;
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- u32 reg;
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-
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- for (i = 0; i < 25; i++) {
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- ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_CMD, ®);
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- if (ret) {
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- dev_err(chip->dev,
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- "Failed to read csr command status: %d\n", ret);
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- return ret;
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- }
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- if (!(reg & LAN9303_SWITCH_CSR_CMD_BUSY))
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- return 0;
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- usleep_range(1000, 2000);
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- }
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-
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- return -EIO;
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+ return lan9303_read_wait(chip, LAN9303_SWITCH_CSR_CMD,
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+ LAN9303_SWITCH_CSR_CMD_BUSY);
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}
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static int lan9303_write_switch_reg(struct lan9303 *chip, u16 regnum, u32 val)
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