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@@ -183,7 +183,7 @@ static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
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const struct mc_firmware_header_v1_0 *hdr;
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const __le32 *fw_data = NULL;
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const __le32 *io_mc_regs = NULL;
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- u32 running, blackout = 0;
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+ u32 running;
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int i, ucode_size, regs_size;
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if (!adev->mc.fw)
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@@ -203,11 +203,6 @@ static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
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running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
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if (running == 0) {
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- if (running) {
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- blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
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- WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
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- }
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-
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/* reset the engine and set to writable */
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WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
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WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
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@@ -239,9 +234,6 @@ static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
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break;
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udelay(1);
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}
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-
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- if (running)
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- WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
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}
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return 0;
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