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@@ -19,6 +19,7 @@
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* file called LICENSE.
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*
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* Contact Information:
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+ * Intel Linux Wireless <ilw@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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*****************************************************************************/
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@@ -45,8 +46,8 @@
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#include "iwl-helpers.h"
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#include "iwl-agn.h"
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#include "iwl-agn-led.h"
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+#include "iwl-agn-hw.h"
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#include "iwl-5000-hw.h"
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-#include "iwl-6000-hw.h"
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/* Highest firmware API version supported */
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#define IWL5000_UCODE_API_MAX 2
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@@ -64,21 +65,8 @@
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#define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
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#define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
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-static const s8 iwl5000_default_queue_to_tx_fifo[] = {
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- IWL_TX_FIFO_VO,
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- IWL_TX_FIFO_VI,
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- IWL_TX_FIFO_BE,
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- IWL_TX_FIFO_BK,
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- IWL50_CMD_FIFO_NUM,
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- IWL_TX_FIFO_UNUSED,
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- IWL_TX_FIFO_UNUSED,
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- IWL_TX_FIFO_UNUSED,
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- IWL_TX_FIFO_UNUSED,
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- IWL_TX_FIFO_UNUSED,
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-};
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-
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/* NIC configuration for 5000 series */
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-void iwl5000_nic_config(struct iwl_priv *priv)
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+static void iwl5000_nic_config(struct iwl_priv *priv)
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{
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unsigned long flags;
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u16 radio_cfg;
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@@ -111,162 +99,6 @@ void iwl5000_nic_config(struct iwl_priv *priv)
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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-
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-/*
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- * EEPROM
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- */
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-static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
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-{
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- u16 offset = 0;
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-
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- if ((address & INDIRECT_ADDRESS) == 0)
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- return address;
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-
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- switch (address & INDIRECT_TYPE_MSK) {
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- case INDIRECT_HOST:
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- offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
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- break;
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- case INDIRECT_GENERAL:
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- offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
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- break;
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- case INDIRECT_REGULATORY:
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- offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
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- break;
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- case INDIRECT_CALIBRATION:
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- offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
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- break;
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- case INDIRECT_PROCESS_ADJST:
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- offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
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- break;
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- case INDIRECT_OTHERS:
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- offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
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- break;
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- default:
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- IWL_ERR(priv, "illegal indirect type: 0x%X\n",
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- address & INDIRECT_TYPE_MSK);
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- break;
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- }
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-
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- /* translate the offset from words to byte */
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- return (address & ADDRESS_MSK) + (offset << 1);
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-}
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-
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-u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
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-{
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- struct iwl_eeprom_calib_hdr {
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- u8 version;
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- u8 pa_type;
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- u16 voltage;
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- } *hdr;
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-
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- hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
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- EEPROM_5000_CALIB_ALL);
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- return hdr->version;
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-
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-}
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-
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-static void iwl5000_gain_computation(struct iwl_priv *priv,
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- u32 average_noise[NUM_RX_CHAINS],
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- u16 min_average_noise_antenna_i,
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- u32 min_average_noise,
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- u8 default_chain)
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-{
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- int i;
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- s32 delta_g;
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- struct iwl_chain_noise_data *data = &priv->chain_noise_data;
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-
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- /*
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- * Find Gain Code for the chains based on "default chain"
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- */
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- for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) {
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- if ((data->disconn_array[i])) {
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- data->delta_gain_code[i] = 0;
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- continue;
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- }
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-
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- delta_g = (priv->cfg->chain_noise_scale *
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- ((s32)average_noise[default_chain] -
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- (s32)average_noise[i])) / 1500;
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-
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- /* bound gain by 2 bits value max, 3rd bit is sign */
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- data->delta_gain_code[i] =
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- min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
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-
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- if (delta_g < 0)
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- /*
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- * set negative sign ...
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- * note to Intel developers: This is uCode API format,
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- * not the format of any internal device registers.
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- * Do not change this format for e.g. 6050 or similar
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- * devices. Change format only if more resolution
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- * (i.e. more than 2 bits magnitude) is needed.
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- */
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- data->delta_gain_code[i] |= (1 << 2);
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- }
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-
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- IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n",
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- data->delta_gain_code[1], data->delta_gain_code[2]);
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-
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- if (!data->radio_write) {
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- struct iwl_calib_chain_noise_gain_cmd cmd;
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-
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- memset(&cmd, 0, sizeof(cmd));
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-
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- cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
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- cmd.hdr.first_group = 0;
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- cmd.hdr.groups_num = 1;
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- cmd.hdr.data_valid = 1;
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- cmd.delta_gain_1 = data->delta_gain_code[1];
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- cmd.delta_gain_2 = data->delta_gain_code[2];
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- iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
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- sizeof(cmd), &cmd, NULL);
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-
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- data->radio_write = 1;
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- data->state = IWL_CHAIN_NOISE_CALIBRATED;
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- }
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-
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- data->chain_noise_a = 0;
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- data->chain_noise_b = 0;
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- data->chain_noise_c = 0;
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- data->chain_signal_a = 0;
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- data->chain_signal_b = 0;
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- data->chain_signal_c = 0;
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- data->beacon_count = 0;
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-}
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-
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-static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
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-{
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- struct iwl_chain_noise_data *data = &priv->chain_noise_data;
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- int ret;
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-
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- if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
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- struct iwl_calib_chain_noise_reset_cmd cmd;
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- memset(&cmd, 0, sizeof(cmd));
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-
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- cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
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- cmd.hdr.first_group = 0;
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- cmd.hdr.groups_num = 1;
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- cmd.hdr.data_valid = 1;
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- ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
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- sizeof(cmd), &cmd);
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- if (ret)
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- IWL_ERR(priv,
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- "Could not send REPLY_PHY_CALIBRATION_CMD\n");
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- data->state = IWL_CHAIN_NOISE_ACCUMULATE;
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- IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
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- }
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-}
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-
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-void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
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- __le32 *tx_flags)
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-{
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- if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
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- (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
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- *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
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- else
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- *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
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-}
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-
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static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
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.min_nrg_cck = 95,
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.max_nrg_cck = 0, /* not used, set to 0 */
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@@ -318,14 +150,6 @@ static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
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.nrg_th_cca = 62,
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};
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-const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
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- size_t offset)
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-{
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- u32 address = eeprom_indirect_address(priv, offset);
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- BUG_ON(address >= priv->cfg->eeprom_size);
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- return &priv->eeprom[address];
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-}
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-
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static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
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{
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const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
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@@ -341,351 +165,10 @@ static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
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priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
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}
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-/*
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- * Calibration
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- */
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-static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
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-{
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- struct iwl_calib_xtal_freq_cmd cmd;
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- __le16 *xtal_calib =
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- (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
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-
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- cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
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- cmd.hdr.first_group = 0;
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- cmd.hdr.groups_num = 1;
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- cmd.hdr.data_valid = 1;
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- cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
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- cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
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- return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
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- (u8 *)&cmd, sizeof(cmd));
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-}
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-
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-static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
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-{
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- struct iwl_calib_cfg_cmd calib_cfg_cmd;
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- struct iwl_host_cmd cmd = {
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- .id = CALIBRATION_CFG_CMD,
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- .len = sizeof(struct iwl_calib_cfg_cmd),
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- .data = &calib_cfg_cmd,
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- };
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-
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- memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
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- calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
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- calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
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- calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
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- calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
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-
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- return iwl_send_cmd(priv, &cmd);
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-}
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-
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-static void iwl5000_rx_calib_result(struct iwl_priv *priv,
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- struct iwl_rx_mem_buffer *rxb)
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-{
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- struct iwl_rx_packet *pkt = rxb_addr(rxb);
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- struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
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- int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
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- int index;
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-
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- /* reduce the size of the length field itself */
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- len -= 4;
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-
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- /* Define the order in which the results will be sent to the runtime
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- * uCode. iwl_send_calib_results sends them in a row according to their
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- * index. We sort them here */
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- switch (hdr->op_code) {
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- case IWL_PHY_CALIBRATE_DC_CMD:
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- index = IWL_CALIB_DC;
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- break;
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- case IWL_PHY_CALIBRATE_LO_CMD:
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- index = IWL_CALIB_LO;
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- break;
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- case IWL_PHY_CALIBRATE_TX_IQ_CMD:
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- index = IWL_CALIB_TX_IQ;
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- break;
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- case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
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- index = IWL_CALIB_TX_IQ_PERD;
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- break;
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- case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
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- index = IWL_CALIB_BASE_BAND;
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- break;
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- default:
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- IWL_ERR(priv, "Unknown calibration notification %d\n",
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- hdr->op_code);
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- return;
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- }
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- iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
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-}
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-
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-static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
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- struct iwl_rx_mem_buffer *rxb)
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-{
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- IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
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- queue_work(priv->workqueue, &priv->restart);
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-}
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-
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-/*
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- * ucode
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- */
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-static int iwl5000_load_section(struct iwl_priv *priv, const char *name,
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- struct fw_desc *image, u32 dst_addr)
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-{
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- dma_addr_t phy_addr = image->p_addr;
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- u32 byte_cnt = image->len;
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- int ret;
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-
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- priv->ucode_write_complete = 0;
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-
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- iwl_write_direct32(priv,
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- FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
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- FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
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-
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- iwl_write_direct32(priv,
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- FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
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-
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- iwl_write_direct32(priv,
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- FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
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- phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
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-
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- iwl_write_direct32(priv,
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- FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
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- (iwl_get_dma_hi_addr(phy_addr)
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- << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
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-
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- iwl_write_direct32(priv,
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- FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
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- 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
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- 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
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- FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
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-
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- iwl_write_direct32(priv,
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- FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
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- FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
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- FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
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- FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
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-
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- IWL_DEBUG_INFO(priv, "%s uCode section being loaded...\n", name);
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- ret = wait_event_interruptible_timeout(priv->wait_command_queue,
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- priv->ucode_write_complete, 5 * HZ);
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- if (ret == -ERESTARTSYS) {
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- IWL_ERR(priv, "Could not load the %s uCode section due "
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- "to interrupt\n", name);
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- return ret;
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- }
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- if (!ret) {
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- IWL_ERR(priv, "Could not load the %s uCode section\n",
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- name);
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- return -ETIMEDOUT;
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- }
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-
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- return 0;
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-}
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-
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-static int iwl5000_load_given_ucode(struct iwl_priv *priv,
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- struct fw_desc *inst_image,
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- struct fw_desc *data_image)
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-{
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- int ret = 0;
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-
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|
|
- ret = iwl5000_load_section(priv, "INST", inst_image,
|
|
|
- IWL50_RTC_INST_LOWER_BOUND);
|
|
|
- if (ret)
|
|
|
- return ret;
|
|
|
-
|
|
|
- return iwl5000_load_section(priv, "DATA", data_image,
|
|
|
- IWL50_RTC_DATA_LOWER_BOUND);
|
|
|
-}
|
|
|
-
|
|
|
-int iwl5000_load_ucode(struct iwl_priv *priv)
|
|
|
-{
|
|
|
- int ret = 0;
|
|
|
-
|
|
|
- /* check whether init ucode should be loaded, or rather runtime ucode */
|
|
|
- if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
|
|
|
- IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
|
|
|
- ret = iwl5000_load_given_ucode(priv,
|
|
|
- &priv->ucode_init, &priv->ucode_init_data);
|
|
|
- if (!ret) {
|
|
|
- IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
|
|
|
- priv->ucode_type = UCODE_INIT;
|
|
|
- }
|
|
|
- } else {
|
|
|
- IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
|
|
|
- "Loading runtime ucode...\n");
|
|
|
- ret = iwl5000_load_given_ucode(priv,
|
|
|
- &priv->ucode_code, &priv->ucode_data);
|
|
|
- if (!ret) {
|
|
|
- IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
|
|
|
- priv->ucode_type = UCODE_RT;
|
|
|
- }
|
|
|
- }
|
|
|
-
|
|
|
- return ret;
|
|
|
-}
|
|
|
-
|
|
|
-void iwl5000_init_alive_start(struct iwl_priv *priv)
|
|
|
-{
|
|
|
- int ret = 0;
|
|
|
-
|
|
|
- /* Check alive response for "valid" sign from uCode */
|
|
|
- if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
|
|
|
- /* We had an error bringing up the hardware, so take it
|
|
|
- * all the way back down so we can try again */
|
|
|
- IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
|
|
|
- goto restart;
|
|
|
- }
|
|
|
-
|
|
|
- /* initialize uCode was loaded... verify inst image.
|
|
|
- * This is a paranoid check, because we would not have gotten the
|
|
|
- * "initialize" alive if code weren't properly loaded. */
|
|
|
- if (iwl_verify_ucode(priv)) {
|
|
|
- /* Runtime instruction load was bad;
|
|
|
- * take it all the way back down so we can try again */
|
|
|
- IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
|
|
|
- goto restart;
|
|
|
- }
|
|
|
-
|
|
|
- ret = priv->cfg->ops->lib->alive_notify(priv);
|
|
|
- if (ret) {
|
|
|
- IWL_WARN(priv,
|
|
|
- "Could not complete ALIVE transition: %d\n", ret);
|
|
|
- goto restart;
|
|
|
- }
|
|
|
-
|
|
|
- iwl5000_send_calib_cfg(priv);
|
|
|
- return;
|
|
|
-
|
|
|
-restart:
|
|
|
- /* real restart (first load init_ucode) */
|
|
|
- queue_work(priv->workqueue, &priv->restart);
|
|
|
-}
|
|
|
-
|
|
|
-static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
|
|
|
- int txq_id, u32 index)
|
|
|
-{
|
|
|
- iwl_write_direct32(priv, HBUS_TARG_WRPTR,
|
|
|
- (index & 0xff) | (txq_id << 8));
|
|
|
- iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
|
|
|
-}
|
|
|
-
|
|
|
-static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
|
|
|
- struct iwl_tx_queue *txq,
|
|
|
- int tx_fifo_id, int scd_retry)
|
|
|
-{
|
|
|
- int txq_id = txq->q.id;
|
|
|
- int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
|
|
|
-
|
|
|
- iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
|
|
|
- (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
|
|
|
- (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
|
|
|
- (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
|
|
|
- IWL50_SCD_QUEUE_STTS_REG_MSK);
|
|
|
-
|
|
|
- txq->sched_retry = scd_retry;
|
|
|
-
|
|
|
- IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
|
|
|
- active ? "Activate" : "Deactivate",
|
|
|
- scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
|
|
|
-}
|
|
|
-
|
|
|
-int iwl5000_alive_notify(struct iwl_priv *priv)
|
|
|
-{
|
|
|
- u32 a;
|
|
|
- unsigned long flags;
|
|
|
- int i, chan;
|
|
|
- u32 reg_val;
|
|
|
-
|
|
|
- spin_lock_irqsave(&priv->lock, flags);
|
|
|
-
|
|
|
- priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
|
|
|
- a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
|
|
|
- for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
|
|
|
- a += 4)
|
|
|
- iwl_write_targ_mem(priv, a, 0);
|
|
|
- for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
|
|
|
- a += 4)
|
|
|
- iwl_write_targ_mem(priv, a, 0);
|
|
|
- for (; a < priv->scd_base_addr +
|
|
|
- IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
|
|
|
- iwl_write_targ_mem(priv, a, 0);
|
|
|
-
|
|
|
- iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
|
|
|
- priv->scd_bc_tbls.dma >> 10);
|
|
|
-
|
|
|
- /* Enable DMA channel */
|
|
|
- for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
|
|
|
- iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
|
|
|
- FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
|
|
|
- FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
|
|
|
-
|
|
|
- /* Update FH chicken bits */
|
|
|
- reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
|
|
|
- iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
|
|
|
- reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
|
|
|
-
|
|
|
- iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
|
|
|
- IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
|
|
|
- iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
|
|
|
-
|
|
|
- /* initiate the queues */
|
|
|
- for (i = 0; i < priv->hw_params.max_txq_num; i++) {
|
|
|
- iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
|
|
|
- iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
|
|
|
- iwl_write_targ_mem(priv, priv->scd_base_addr +
|
|
|
- IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
|
|
|
- iwl_write_targ_mem(priv, priv->scd_base_addr +
|
|
|
- IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
|
|
|
- sizeof(u32),
|
|
|
- ((SCD_WIN_SIZE <<
|
|
|
- IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
|
|
|
- IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
|
|
|
- ((SCD_FRAME_LIMIT <<
|
|
|
- IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
|
|
|
- IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
|
|
|
- }
|
|
|
-
|
|
|
- iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
|
|
|
- IWL_MASK(0, priv->hw_params.max_txq_num));
|
|
|
-
|
|
|
- /* Activate all Tx DMA/FIFO channels */
|
|
|
- priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
|
|
|
-
|
|
|
- iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
|
|
|
-
|
|
|
- /* make sure all queue are not stopped */
|
|
|
- memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
|
|
|
- for (i = 0; i < 4; i++)
|
|
|
- atomic_set(&priv->queue_stop_count[i], 0);
|
|
|
-
|
|
|
- /* reset to 0 to enable all the queue first */
|
|
|
- priv->txq_ctx_active_msk = 0;
|
|
|
- /* map qos queues to fifos one-to-one */
|
|
|
- BUILD_BUG_ON(ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo) != 10);
|
|
|
-
|
|
|
- for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
|
|
|
- int ac = iwl5000_default_queue_to_tx_fifo[i];
|
|
|
-
|
|
|
- iwl_txq_ctx_activate(priv, i);
|
|
|
-
|
|
|
- if (ac == IWL_TX_FIFO_UNUSED)
|
|
|
- continue;
|
|
|
-
|
|
|
- iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
|
|
|
- }
|
|
|
-
|
|
|
- spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
-
|
|
|
- iwl_send_wimax_coex(priv);
|
|
|
-
|
|
|
- iwl5000_set_Xtal_calib(priv);
|
|
|
- iwl_send_calib_results(priv);
|
|
|
-
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
-int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
|
|
|
+static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
|
|
|
{
|
|
|
if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
|
|
|
- priv->cfg->mod_params->num_of_queues <= IWL50_NUM_QUEUES)
|
|
|
+ priv->cfg->mod_params->num_of_queues <= IWLAGN_NUM_QUEUES)
|
|
|
priv->cfg->num_of_queues =
|
|
|
priv->cfg->mod_params->num_of_queues;
|
|
|
|
|
|
@@ -693,13 +176,13 @@ int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
|
|
|
priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
|
|
|
priv->hw_params.scd_bc_tbls_size =
|
|
|
priv->cfg->num_of_queues *
|
|
|
- sizeof(struct iwl5000_scd_bc_tbl);
|
|
|
+ sizeof(struct iwlagn_scd_bc_tbl);
|
|
|
priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
|
|
|
priv->hw_params.max_stations = IWL5000_STATION_COUNT;
|
|
|
priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
|
|
|
|
|
|
- priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
|
|
|
- priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
|
|
|
+ priv->hw_params.max_data_size = IWLAGN_RTC_DATA_SIZE;
|
|
|
+ priv->hw_params.max_inst_size = IWLAGN_RTC_INST_SIZE;
|
|
|
|
|
|
priv->hw_params.max_bsm_size = 0;
|
|
|
priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
|
|
|
@@ -740,547 +223,6 @@ int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
-/**
|
|
|
- * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
|
|
|
- */
|
|
|
-void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
|
|
|
- struct iwl_tx_queue *txq,
|
|
|
- u16 byte_cnt)
|
|
|
-{
|
|
|
- struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
|
|
|
- int write_ptr = txq->q.write_ptr;
|
|
|
- int txq_id = txq->q.id;
|
|
|
- u8 sec_ctl = 0;
|
|
|
- u8 sta_id = 0;
|
|
|
- u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
|
|
|
- __le16 bc_ent;
|
|
|
-
|
|
|
- WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
|
|
|
-
|
|
|
- if (txq_id != IWL_CMD_QUEUE_NUM) {
|
|
|
- sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
|
|
|
- sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
|
|
|
-
|
|
|
- switch (sec_ctl & TX_CMD_SEC_MSK) {
|
|
|
- case TX_CMD_SEC_CCM:
|
|
|
- len += CCMP_MIC_LEN;
|
|
|
- break;
|
|
|
- case TX_CMD_SEC_TKIP:
|
|
|
- len += TKIP_ICV_LEN;
|
|
|
- break;
|
|
|
- case TX_CMD_SEC_WEP:
|
|
|
- len += WEP_IV_LEN + WEP_ICV_LEN;
|
|
|
- break;
|
|
|
- }
|
|
|
- }
|
|
|
-
|
|
|
- bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
|
|
|
-
|
|
|
- scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
|
|
|
-
|
|
|
- if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
|
|
|
- scd_bc_tbl[txq_id].
|
|
|
- tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
|
|
|
-}
|
|
|
-
|
|
|
-void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
|
|
|
- struct iwl_tx_queue *txq)
|
|
|
-{
|
|
|
- struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
|
|
|
- int txq_id = txq->q.id;
|
|
|
- int read_ptr = txq->q.read_ptr;
|
|
|
- u8 sta_id = 0;
|
|
|
- __le16 bc_ent;
|
|
|
-
|
|
|
- WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
|
|
|
-
|
|
|
- if (txq_id != IWL_CMD_QUEUE_NUM)
|
|
|
- sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
|
|
|
-
|
|
|
- bc_ent = cpu_to_le16(1 | (sta_id << 12));
|
|
|
- scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
|
|
|
-
|
|
|
- if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
|
|
|
- scd_bc_tbl[txq_id].
|
|
|
- tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
|
|
|
-}
|
|
|
-
|
|
|
-static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
|
|
|
- u16 txq_id)
|
|
|
-{
|
|
|
- u32 tbl_dw_addr;
|
|
|
- u32 tbl_dw;
|
|
|
- u16 scd_q2ratid;
|
|
|
-
|
|
|
- scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
|
|
|
-
|
|
|
- tbl_dw_addr = priv->scd_base_addr +
|
|
|
- IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
|
|
|
-
|
|
|
- tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
|
|
|
-
|
|
|
- if (txq_id & 0x1)
|
|
|
- tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
|
|
|
- else
|
|
|
- tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
|
|
|
-
|
|
|
- iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
|
|
|
-
|
|
|
- return 0;
|
|
|
-}
|
|
|
-static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
|
|
|
-{
|
|
|
- /* Simply stop the queue, but don't change any configuration;
|
|
|
- * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
|
|
|
- iwl_write_prph(priv,
|
|
|
- IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
|
|
|
- (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
|
|
|
- (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
|
|
|
-}
|
|
|
-
|
|
|
-int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
|
|
|
- int tx_fifo, int sta_id, int tid, u16 ssn_idx)
|
|
|
-{
|
|
|
- unsigned long flags;
|
|
|
- u16 ra_tid;
|
|
|
-
|
|
|
- if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
|
|
|
- (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
|
|
|
- <= txq_id)) {
|
|
|
- IWL_WARN(priv,
|
|
|
- "queue number out of range: %d, must be %d to %d\n",
|
|
|
- txq_id, IWL50_FIRST_AMPDU_QUEUE,
|
|
|
- IWL50_FIRST_AMPDU_QUEUE +
|
|
|
- priv->cfg->num_of_ampdu_queues - 1);
|
|
|
- return -EINVAL;
|
|
|
- }
|
|
|
-
|
|
|
- ra_tid = BUILD_RAxTID(sta_id, tid);
|
|
|
-
|
|
|
- /* Modify device's station table to Tx this TID */
|
|
|
- iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
|
|
|
-
|
|
|
- spin_lock_irqsave(&priv->lock, flags);
|
|
|
-
|
|
|
- /* Stop this Tx queue before configuring it */
|
|
|
- iwl5000_tx_queue_stop_scheduler(priv, txq_id);
|
|
|
-
|
|
|
- /* Map receiver-address / traffic-ID to this queue */
|
|
|
- iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
|
|
|
-
|
|
|
- /* Set this queue as a chain-building queue */
|
|
|
- iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
|
|
|
-
|
|
|
- /* enable aggregations for the queue */
|
|
|
- iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
|
|
|
-
|
|
|
- /* Place first TFD at index corresponding to start sequence number.
|
|
|
- * Assumes that ssn_idx is valid (!= 0xFFF) */
|
|
|
- priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
|
|
|
- priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
|
|
|
- iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
|
|
|
-
|
|
|
- /* Set up Tx window size and frame limit for this queue */
|
|
|
- iwl_write_targ_mem(priv, priv->scd_base_addr +
|
|
|
- IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
|
|
|
- sizeof(u32),
|
|
|
- ((SCD_WIN_SIZE <<
|
|
|
- IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
|
|
|
- IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
|
|
|
- ((SCD_FRAME_LIMIT <<
|
|
|
- IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
|
|
|
- IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
|
|
|
-
|
|
|
- iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
|
|
|
-
|
|
|
- /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
|
|
|
- iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
|
|
|
-
|
|
|
- spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
-
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
-int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
|
|
|
- u16 ssn_idx, u8 tx_fifo)
|
|
|
-{
|
|
|
- if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
|
|
|
- (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
|
|
|
- <= txq_id)) {
|
|
|
- IWL_ERR(priv,
|
|
|
- "queue number out of range: %d, must be %d to %d\n",
|
|
|
- txq_id, IWL50_FIRST_AMPDU_QUEUE,
|
|
|
- IWL50_FIRST_AMPDU_QUEUE +
|
|
|
- priv->cfg->num_of_ampdu_queues - 1);
|
|
|
- return -EINVAL;
|
|
|
- }
|
|
|
-
|
|
|
- iwl5000_tx_queue_stop_scheduler(priv, txq_id);
|
|
|
-
|
|
|
- iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
|
|
|
-
|
|
|
- priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
|
|
|
- priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
|
|
|
- /* supposes that ssn_idx is valid (!= 0xFFF) */
|
|
|
- iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
|
|
|
-
|
|
|
- iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
|
|
|
- iwl_txq_ctx_deactivate(priv, txq_id);
|
|
|
- iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
|
|
|
-
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
-u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
|
|
|
-{
|
|
|
- u16 size = (u16)sizeof(struct iwl_addsta_cmd);
|
|
|
- struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
|
|
|
- memcpy(addsta, cmd, size);
|
|
|
- /* resrved in 5000 */
|
|
|
- addsta->rate_n_flags = cpu_to_le16(0);
|
|
|
- return size;
|
|
|
-}
|
|
|
-
|
|
|
-
|
|
|
-/*
|
|
|
- * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
|
|
|
- * must be called under priv->lock and mac access
|
|
|
- */
|
|
|
-void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
|
|
|
-{
|
|
|
- iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
|
|
|
-}
|
|
|
-
|
|
|
-
|
|
|
-static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
|
|
|
-{
|
|
|
- return le32_to_cpup((__le32 *)&tx_resp->status +
|
|
|
- tx_resp->frame_count) & MAX_SN;
|
|
|
-}
|
|
|
-
|
|
|
-static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
|
|
|
- struct iwl_ht_agg *agg,
|
|
|
- struct iwl5000_tx_resp *tx_resp,
|
|
|
- int txq_id, u16 start_idx)
|
|
|
-{
|
|
|
- u16 status;
|
|
|
- struct agg_tx_status *frame_status = &tx_resp->status;
|
|
|
- struct ieee80211_tx_info *info = NULL;
|
|
|
- struct ieee80211_hdr *hdr = NULL;
|
|
|
- u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
|
|
|
- int i, sh, idx;
|
|
|
- u16 seq;
|
|
|
-
|
|
|
- if (agg->wait_for_ba)
|
|
|
- IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
|
|
|
-
|
|
|
- agg->frame_count = tx_resp->frame_count;
|
|
|
- agg->start_idx = start_idx;
|
|
|
- agg->rate_n_flags = rate_n_flags;
|
|
|
- agg->bitmap = 0;
|
|
|
-
|
|
|
- /* # frames attempted by Tx command */
|
|
|
- if (agg->frame_count == 1) {
|
|
|
- /* Only one frame was attempted; no block-ack will arrive */
|
|
|
- status = le16_to_cpu(frame_status[0].status);
|
|
|
- idx = start_idx;
|
|
|
-
|
|
|
- /* FIXME: code repetition */
|
|
|
- IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
|
|
|
- agg->frame_count, agg->start_idx, idx);
|
|
|
-
|
|
|
- info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
|
|
|
- info->status.rates[0].count = tx_resp->failure_frame + 1;
|
|
|
- info->flags &= ~IEEE80211_TX_CTL_AMPDU;
|
|
|
- info->flags |= iwl_tx_status_to_mac80211(status);
|
|
|
- iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
|
|
|
-
|
|
|
- /* FIXME: code repetition end */
|
|
|
-
|
|
|
- IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
|
|
|
- status & 0xff, tx_resp->failure_frame);
|
|
|
- IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
|
|
|
-
|
|
|
- agg->wait_for_ba = 0;
|
|
|
- } else {
|
|
|
- /* Two or more frames were attempted; expect block-ack */
|
|
|
- u64 bitmap = 0;
|
|
|
- int start = agg->start_idx;
|
|
|
-
|
|
|
- /* Construct bit-map of pending frames within Tx window */
|
|
|
- for (i = 0; i < agg->frame_count; i++) {
|
|
|
- u16 sc;
|
|
|
- status = le16_to_cpu(frame_status[i].status);
|
|
|
- seq = le16_to_cpu(frame_status[i].sequence);
|
|
|
- idx = SEQ_TO_INDEX(seq);
|
|
|
- txq_id = SEQ_TO_QUEUE(seq);
|
|
|
-
|
|
|
- if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
|
|
|
- AGG_TX_STATE_ABORT_MSK))
|
|
|
- continue;
|
|
|
-
|
|
|
- IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
|
|
|
- agg->frame_count, txq_id, idx);
|
|
|
-
|
|
|
- hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
|
|
|
- if (!hdr) {
|
|
|
- IWL_ERR(priv,
|
|
|
- "BUG_ON idx doesn't point to valid skb"
|
|
|
- " idx=%d, txq_id=%d\n", idx, txq_id);
|
|
|
- return -1;
|
|
|
- }
|
|
|
-
|
|
|
- sc = le16_to_cpu(hdr->seq_ctrl);
|
|
|
- if (idx != (SEQ_TO_SN(sc) & 0xff)) {
|
|
|
- IWL_ERR(priv,
|
|
|
- "BUG_ON idx doesn't match seq control"
|
|
|
- " idx=%d, seq_idx=%d, seq=%d\n",
|
|
|
- idx, SEQ_TO_SN(sc),
|
|
|
- hdr->seq_ctrl);
|
|
|
- return -1;
|
|
|
- }
|
|
|
-
|
|
|
- IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
|
|
|
- i, idx, SEQ_TO_SN(sc));
|
|
|
-
|
|
|
- sh = idx - start;
|
|
|
- if (sh > 64) {
|
|
|
- sh = (start - idx) + 0xff;
|
|
|
- bitmap = bitmap << sh;
|
|
|
- sh = 0;
|
|
|
- start = idx;
|
|
|
- } else if (sh < -64)
|
|
|
- sh = 0xff - (start - idx);
|
|
|
- else if (sh < 0) {
|
|
|
- sh = start - idx;
|
|
|
- start = idx;
|
|
|
- bitmap = bitmap << sh;
|
|
|
- sh = 0;
|
|
|
- }
|
|
|
- bitmap |= 1ULL << sh;
|
|
|
- IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
|
|
|
- start, (unsigned long long)bitmap);
|
|
|
- }
|
|
|
-
|
|
|
- agg->bitmap = bitmap;
|
|
|
- agg->start_idx = start;
|
|
|
- IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
|
|
|
- agg->frame_count, agg->start_idx,
|
|
|
- (unsigned long long)agg->bitmap);
|
|
|
-
|
|
|
- if (bitmap)
|
|
|
- agg->wait_for_ba = 1;
|
|
|
- }
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
-static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
|
|
|
- struct iwl_rx_mem_buffer *rxb)
|
|
|
-{
|
|
|
- struct iwl_rx_packet *pkt = rxb_addr(rxb);
|
|
|
- u16 sequence = le16_to_cpu(pkt->hdr.sequence);
|
|
|
- int txq_id = SEQ_TO_QUEUE(sequence);
|
|
|
- int index = SEQ_TO_INDEX(sequence);
|
|
|
- struct iwl_tx_queue *txq = &priv->txq[txq_id];
|
|
|
- struct ieee80211_tx_info *info;
|
|
|
- struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
|
|
|
- u32 status = le16_to_cpu(tx_resp->status.status);
|
|
|
- int tid;
|
|
|
- int sta_id;
|
|
|
- int freed;
|
|
|
-
|
|
|
- if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
|
|
|
- IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
|
|
|
- "is out of range [0-%d] %d %d\n", txq_id,
|
|
|
- index, txq->q.n_bd, txq->q.write_ptr,
|
|
|
- txq->q.read_ptr);
|
|
|
- return;
|
|
|
- }
|
|
|
-
|
|
|
- info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
|
|
|
- memset(&info->status, 0, sizeof(info->status));
|
|
|
-
|
|
|
- tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
|
|
|
- sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
|
|
|
-
|
|
|
- if (txq->sched_retry) {
|
|
|
- const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
|
|
|
- struct iwl_ht_agg *agg = NULL;
|
|
|
-
|
|
|
- agg = &priv->stations[sta_id].tid[tid].agg;
|
|
|
-
|
|
|
- iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
|
|
|
-
|
|
|
- /* check if BAR is needed */
|
|
|
- if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
|
|
|
- info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
|
|
|
-
|
|
|
- if (txq->q.read_ptr != (scd_ssn & 0xff)) {
|
|
|
- index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
|
|
|
- IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
|
|
|
- "scd_ssn=%d idx=%d txq=%d swq=%d\n",
|
|
|
- scd_ssn , index, txq_id, txq->swq_id);
|
|
|
-
|
|
|
- freed = iwl_tx_queue_reclaim(priv, txq_id, index);
|
|
|
- iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
|
|
|
-
|
|
|
- if (priv->mac80211_registered &&
|
|
|
- (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
|
|
|
- (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
|
|
|
- if (agg->state == IWL_AGG_OFF)
|
|
|
- iwl_wake_queue(priv, txq_id);
|
|
|
- else
|
|
|
- iwl_wake_queue(priv, txq->swq_id);
|
|
|
- }
|
|
|
- }
|
|
|
- } else {
|
|
|
- BUG_ON(txq_id != txq->swq_id);
|
|
|
-
|
|
|
- info->status.rates[0].count = tx_resp->failure_frame + 1;
|
|
|
- info->flags |= iwl_tx_status_to_mac80211(status);
|
|
|
- iwl_hwrate_to_tx_control(priv,
|
|
|
- le32_to_cpu(tx_resp->rate_n_flags),
|
|
|
- info);
|
|
|
-
|
|
|
- IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
|
|
|
- "0x%x retries %d\n",
|
|
|
- txq_id,
|
|
|
- iwl_get_tx_fail_reason(status), status,
|
|
|
- le32_to_cpu(tx_resp->rate_n_flags),
|
|
|
- tx_resp->failure_frame);
|
|
|
-
|
|
|
- freed = iwl_tx_queue_reclaim(priv, txq_id, index);
|
|
|
- iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
|
|
|
-
|
|
|
- if (priv->mac80211_registered &&
|
|
|
- (iwl_queue_space(&txq->q) > txq->q.low_mark))
|
|
|
- iwl_wake_queue(priv, txq_id);
|
|
|
- }
|
|
|
-
|
|
|
- iwl_txq_check_empty(priv, sta_id, tid, txq_id);
|
|
|
-
|
|
|
- if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
|
|
|
- IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
|
|
|
-}
|
|
|
-
|
|
|
-/* Currently 5000 is the superset of everything */
|
|
|
-u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
|
|
|
-{
|
|
|
- return len;
|
|
|
-}
|
|
|
-
|
|
|
-void iwl5000_setup_deferred_work(struct iwl_priv *priv)
|
|
|
-{
|
|
|
- /* in 5000 the tx power calibration is done in uCode */
|
|
|
- priv->disable_tx_power_cal = 1;
|
|
|
-}
|
|
|
-
|
|
|
-void iwl5000_rx_handler_setup(struct iwl_priv *priv)
|
|
|
-{
|
|
|
- /* init calibration handlers */
|
|
|
- priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
|
|
|
- iwl5000_rx_calib_result;
|
|
|
- priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
|
|
|
- iwl5000_rx_calib_complete;
|
|
|
- priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
|
|
|
-}
|
|
|
-
|
|
|
-
|
|
|
-int iwl5000_hw_valid_rtc_data_addr(u32 addr)
|
|
|
-{
|
|
|
- return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
|
|
|
- (addr < IWL50_RTC_DATA_UPPER_BOUND);
|
|
|
-}
|
|
|
-
|
|
|
-static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
|
|
|
-{
|
|
|
- int ret = 0;
|
|
|
- struct iwl5000_rxon_assoc_cmd rxon_assoc;
|
|
|
- const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
|
|
|
- const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
|
|
|
-
|
|
|
- if ((rxon1->flags == rxon2->flags) &&
|
|
|
- (rxon1->filter_flags == rxon2->filter_flags) &&
|
|
|
- (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
|
|
|
- (rxon1->ofdm_ht_single_stream_basic_rates ==
|
|
|
- rxon2->ofdm_ht_single_stream_basic_rates) &&
|
|
|
- (rxon1->ofdm_ht_dual_stream_basic_rates ==
|
|
|
- rxon2->ofdm_ht_dual_stream_basic_rates) &&
|
|
|
- (rxon1->ofdm_ht_triple_stream_basic_rates ==
|
|
|
- rxon2->ofdm_ht_triple_stream_basic_rates) &&
|
|
|
- (rxon1->acquisition_data == rxon2->acquisition_data) &&
|
|
|
- (rxon1->rx_chain == rxon2->rx_chain) &&
|
|
|
- (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
|
|
|
- IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
|
|
|
- return 0;
|
|
|
- }
|
|
|
-
|
|
|
- rxon_assoc.flags = priv->staging_rxon.flags;
|
|
|
- rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
|
|
|
- rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
|
|
|
- rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
|
|
|
- rxon_assoc.reserved1 = 0;
|
|
|
- rxon_assoc.reserved2 = 0;
|
|
|
- rxon_assoc.reserved3 = 0;
|
|
|
- rxon_assoc.ofdm_ht_single_stream_basic_rates =
|
|
|
- priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
|
|
|
- rxon_assoc.ofdm_ht_dual_stream_basic_rates =
|
|
|
- priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
|
|
|
- rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
|
|
|
- rxon_assoc.ofdm_ht_triple_stream_basic_rates =
|
|
|
- priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
|
|
|
- rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
|
|
|
-
|
|
|
- ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
|
|
|
- sizeof(rxon_assoc), &rxon_assoc, NULL);
|
|
|
- if (ret)
|
|
|
- return ret;
|
|
|
-
|
|
|
- return ret;
|
|
|
-}
|
|
|
-int iwl5000_send_tx_power(struct iwl_priv *priv)
|
|
|
-{
|
|
|
- struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
|
|
|
- u8 tx_ant_cfg_cmd;
|
|
|
-
|
|
|
- /* half dBm need to multiply */
|
|
|
- tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
|
|
|
-
|
|
|
- if (priv->tx_power_lmt_in_half_dbm &&
|
|
|
- priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
|
|
|
- /*
|
|
|
- * For the newer devices which using enhanced/extend tx power
|
|
|
- * table in EEPROM, the format is in half dBm. driver need to
|
|
|
- * convert to dBm format before report to mac80211.
|
|
|
- * By doing so, there is a possibility of 1/2 dBm resolution
|
|
|
- * lost. driver will perform "round-up" operation before
|
|
|
- * reporting, but it will cause 1/2 dBm tx power over the
|
|
|
- * regulatory limit. Perform the checking here, if the
|
|
|
- * "tx_power_user_lmt" is higher than EEPROM value (in
|
|
|
- * half-dBm format), lower the tx power based on EEPROM
|
|
|
- */
|
|
|
- tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
|
|
|
- }
|
|
|
- tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
|
|
|
- tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
|
|
|
-
|
|
|
- if (IWL_UCODE_API(priv->ucode_ver) == 1)
|
|
|
- tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
|
|
|
- else
|
|
|
- tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
|
|
|
-
|
|
|
- return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
|
|
|
- sizeof(tx_power_cmd), &tx_power_cmd,
|
|
|
- NULL);
|
|
|
-}
|
|
|
-
|
|
|
-void iwl5000_temperature(struct iwl_priv *priv)
|
|
|
-{
|
|
|
- /* store temperature from statistics (in Celsius) */
|
|
|
- priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
|
|
|
- iwl_tt_handler(priv);
|
|
|
-}
|
|
|
-
|
|
|
static void iwl5150_temperature(struct iwl_priv *priv)
|
|
|
{
|
|
|
u32 vt = 0;
|
|
|
@@ -1293,100 +235,6 @@ static void iwl5150_temperature(struct iwl_priv *priv)
|
|
|
iwl_tt_handler(priv);
|
|
|
}
|
|
|
|
|
|
-/* Calc max signal level (dBm) among 3 possible receivers */
|
|
|
-int iwl5000_calc_rssi(struct iwl_priv *priv,
|
|
|
- struct iwl_rx_phy_res *rx_resp)
|
|
|
-{
|
|
|
- /* data from PHY/DSP regarding signal strength, etc.,
|
|
|
- * contents are always there, not configurable by host
|
|
|
- */
|
|
|
- struct iwl5000_non_cfg_phy *ncphy =
|
|
|
- (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
|
|
|
- u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
|
|
|
- u8 agc;
|
|
|
-
|
|
|
- val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
|
|
|
- agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
|
|
|
-
|
|
|
- /* Find max rssi among 3 possible receivers.
|
|
|
- * These values are measured by the digital signal processor (DSP).
|
|
|
- * They should stay fairly constant even as the signal strength varies,
|
|
|
- * if the radio's automatic gain control (AGC) is working right.
|
|
|
- * AGC value (see below) will provide the "interesting" info.
|
|
|
- */
|
|
|
- val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
|
|
|
- rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
|
|
|
- rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
|
|
|
- val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
|
|
|
- rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
|
|
|
-
|
|
|
- max_rssi = max_t(u32, rssi_a, rssi_b);
|
|
|
- max_rssi = max_t(u32, max_rssi, rssi_c);
|
|
|
-
|
|
|
- IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
|
|
|
- rssi_a, rssi_b, rssi_c, max_rssi, agc);
|
|
|
-
|
|
|
- /* dBm = max_rssi dB - agc dB - constant.
|
|
|
- * Higher AGC (higher radio gain) means lower signal. */
|
|
|
- return max_rssi - agc - IWL49_RSSI_OFFSET;
|
|
|
-}
|
|
|
-
|
|
|
-static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant)
|
|
|
-{
|
|
|
- struct iwl_tx_ant_config_cmd tx_ant_cmd = {
|
|
|
- .valid = cpu_to_le32(valid_tx_ant),
|
|
|
- };
|
|
|
-
|
|
|
- if (IWL_UCODE_API(priv->ucode_ver) > 1) {
|
|
|
- IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant);
|
|
|
- return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD,
|
|
|
- sizeof(struct iwl_tx_ant_config_cmd),
|
|
|
- &tx_ant_cmd);
|
|
|
- } else {
|
|
|
- IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n");
|
|
|
- return -EOPNOTSUPP;
|
|
|
- }
|
|
|
-}
|
|
|
-
|
|
|
-
|
|
|
-#define IWL5000_UCODE_GET(item) \
|
|
|
-static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
|
|
|
- u32 api_ver) \
|
|
|
-{ \
|
|
|
- if (api_ver <= 2) \
|
|
|
- return le32_to_cpu(ucode->u.v1.item); \
|
|
|
- return le32_to_cpu(ucode->u.v2.item); \
|
|
|
-}
|
|
|
-
|
|
|
-static u32 iwl5000_ucode_get_header_size(u32 api_ver)
|
|
|
-{
|
|
|
- if (api_ver <= 2)
|
|
|
- return UCODE_HEADER_SIZE(1);
|
|
|
- return UCODE_HEADER_SIZE(2);
|
|
|
-}
|
|
|
-
|
|
|
-static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
|
|
|
- u32 api_ver)
|
|
|
-{
|
|
|
- if (api_ver <= 2)
|
|
|
- return 0;
|
|
|
- return le32_to_cpu(ucode->u.v2.build);
|
|
|
-}
|
|
|
-
|
|
|
-static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
|
|
|
- u32 api_ver)
|
|
|
-{
|
|
|
- if (api_ver <= 2)
|
|
|
- return (u8 *) ucode->u.v1.data;
|
|
|
- return (u8 *) ucode->u.v2.data;
|
|
|
-}
|
|
|
-
|
|
|
-IWL5000_UCODE_GET(inst_size);
|
|
|
-IWL5000_UCODE_GET(data_size);
|
|
|
-IWL5000_UCODE_GET(init_size);
|
|
|
-IWL5000_UCODE_GET(init_data_size);
|
|
|
-IWL5000_UCODE_GET(boot_size);
|
|
|
-
|
|
|
static int iwl5000_hw_channel_switch(struct iwl_priv *priv, u16 channel)
|
|
|
{
|
|
|
struct iwl5000_channel_switch_cmd cmd;
|
|
|
@@ -1419,54 +267,27 @@ static int iwl5000_hw_channel_switch(struct iwl_priv *priv, u16 channel)
|
|
|
return iwl_send_cmd_sync(priv, &hcmd);
|
|
|
}
|
|
|
|
|
|
-struct iwl_hcmd_ops iwl5000_hcmd = {
|
|
|
- .rxon_assoc = iwl5000_send_rxon_assoc,
|
|
|
- .commit_rxon = iwl_commit_rxon,
|
|
|
- .set_rxon_chain = iwl_set_rxon_chain,
|
|
|
- .set_tx_ant = iwl5000_send_tx_ant_config,
|
|
|
-};
|
|
|
-
|
|
|
-struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
|
|
|
- .get_hcmd_size = iwl5000_get_hcmd_size,
|
|
|
- .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
|
|
|
- .gain_computation = iwl5000_gain_computation,
|
|
|
- .chain_noise_reset = iwl5000_chain_noise_reset,
|
|
|
- .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
|
|
|
- .calc_rssi = iwl5000_calc_rssi,
|
|
|
-};
|
|
|
-
|
|
|
-struct iwl_ucode_ops iwl5000_ucode = {
|
|
|
- .get_header_size = iwl5000_ucode_get_header_size,
|
|
|
- .get_build = iwl5000_ucode_get_build,
|
|
|
- .get_inst_size = iwl5000_ucode_get_inst_size,
|
|
|
- .get_data_size = iwl5000_ucode_get_data_size,
|
|
|
- .get_init_size = iwl5000_ucode_get_init_size,
|
|
|
- .get_init_data_size = iwl5000_ucode_get_init_data_size,
|
|
|
- .get_boot_size = iwl5000_ucode_get_boot_size,
|
|
|
- .get_data = iwl5000_ucode_get_data,
|
|
|
-};
|
|
|
-
|
|
|
-struct iwl_lib_ops iwl5000_lib = {
|
|
|
+static struct iwl_lib_ops iwl5000_lib = {
|
|
|
.set_hw_params = iwl5000_hw_set_hw_params,
|
|
|
- .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
|
|
|
- .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
|
|
|
- .txq_set_sched = iwl5000_txq_set_sched,
|
|
|
- .txq_agg_enable = iwl5000_txq_agg_enable,
|
|
|
- .txq_agg_disable = iwl5000_txq_agg_disable,
|
|
|
+ .txq_update_byte_cnt_tbl = iwlagn_txq_update_byte_cnt_tbl,
|
|
|
+ .txq_inval_byte_cnt_tbl = iwlagn_txq_inval_byte_cnt_tbl,
|
|
|
+ .txq_set_sched = iwlagn_txq_set_sched,
|
|
|
+ .txq_agg_enable = iwlagn_txq_agg_enable,
|
|
|
+ .txq_agg_disable = iwlagn_txq_agg_disable,
|
|
|
.txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
|
|
|
.txq_free_tfd = iwl_hw_txq_free_tfd,
|
|
|
.txq_init = iwl_hw_tx_queue_init,
|
|
|
- .rx_handler_setup = iwl5000_rx_handler_setup,
|
|
|
- .setup_deferred_work = iwl5000_setup_deferred_work,
|
|
|
- .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
|
|
|
+ .rx_handler_setup = iwlagn_rx_handler_setup,
|
|
|
+ .setup_deferred_work = iwlagn_setup_deferred_work,
|
|
|
+ .is_valid_rtc_data_addr = iwlagn_hw_valid_rtc_data_addr,
|
|
|
.dump_nic_event_log = iwl_dump_nic_event_log,
|
|
|
.dump_nic_error_log = iwl_dump_nic_error_log,
|
|
|
.dump_csr = iwl_dump_csr,
|
|
|
.dump_fh = iwl_dump_fh,
|
|
|
- .load_ucode = iwl5000_load_ucode,
|
|
|
- .init_alive_start = iwl5000_init_alive_start,
|
|
|
- .alive_notify = iwl5000_alive_notify,
|
|
|
- .send_tx_power = iwl5000_send_tx_power,
|
|
|
+ .load_ucode = iwlagn_load_ucode,
|
|
|
+ .init_alive_start = iwlagn_init_alive_start,
|
|
|
+ .alive_notify = iwlagn_alive_notify,
|
|
|
+ .send_tx_power = iwlagn_send_tx_power,
|
|
|
.update_chain_flags = iwl_update_chain_flags,
|
|
|
.set_channel_switch = iwl5000_hw_channel_switch,
|
|
|
.apm_ops = {
|
|
|
@@ -1477,25 +298,25 @@ struct iwl_lib_ops iwl5000_lib = {
|
|
|
},
|
|
|
.eeprom_ops = {
|
|
|
.regulatory_bands = {
|
|
|
- EEPROM_5000_REG_BAND_1_CHANNELS,
|
|
|
- EEPROM_5000_REG_BAND_2_CHANNELS,
|
|
|
- EEPROM_5000_REG_BAND_3_CHANNELS,
|
|
|
- EEPROM_5000_REG_BAND_4_CHANNELS,
|
|
|
- EEPROM_5000_REG_BAND_5_CHANNELS,
|
|
|
- EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
|
|
|
- EEPROM_5000_REG_BAND_52_HT40_CHANNELS
|
|
|
+ EEPROM_REG_BAND_1_CHANNELS,
|
|
|
+ EEPROM_REG_BAND_2_CHANNELS,
|
|
|
+ EEPROM_REG_BAND_3_CHANNELS,
|
|
|
+ EEPROM_REG_BAND_4_CHANNELS,
|
|
|
+ EEPROM_REG_BAND_5_CHANNELS,
|
|
|
+ EEPROM_REG_BAND_24_HT40_CHANNELS,
|
|
|
+ EEPROM_REG_BAND_52_HT40_CHANNELS
|
|
|
},
|
|
|
.verify_signature = iwlcore_eeprom_verify_signature,
|
|
|
.acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
|
|
|
.release_semaphore = iwlcore_eeprom_release_semaphore,
|
|
|
- .calib_version = iwl5000_eeprom_calib_version,
|
|
|
- .query_addr = iwl5000_eeprom_query_addr,
|
|
|
+ .calib_version = iwlagn_eeprom_calib_version,
|
|
|
+ .query_addr = iwlagn_eeprom_query_addr,
|
|
|
},
|
|
|
.post_associate = iwl_post_associate,
|
|
|
.isr = iwl_isr_ict,
|
|
|
.config_ap = iwl_config_ap,
|
|
|
.temp_ops = {
|
|
|
- .temperature = iwl5000_temperature,
|
|
|
+ .temperature = iwlagn_temperature,
|
|
|
.set_ct_kill = iwl5000_set_ct_threshold,
|
|
|
},
|
|
|
.add_bcast_station = iwl_add_bcast_station,
|
|
|
@@ -1506,24 +327,24 @@ struct iwl_lib_ops iwl5000_lib = {
|
|
|
|
|
|
static struct iwl_lib_ops iwl5150_lib = {
|
|
|
.set_hw_params = iwl5000_hw_set_hw_params,
|
|
|
- .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
|
|
|
- .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
|
|
|
- .txq_set_sched = iwl5000_txq_set_sched,
|
|
|
- .txq_agg_enable = iwl5000_txq_agg_enable,
|
|
|
- .txq_agg_disable = iwl5000_txq_agg_disable,
|
|
|
+ .txq_update_byte_cnt_tbl = iwlagn_txq_update_byte_cnt_tbl,
|
|
|
+ .txq_inval_byte_cnt_tbl = iwlagn_txq_inval_byte_cnt_tbl,
|
|
|
+ .txq_set_sched = iwlagn_txq_set_sched,
|
|
|
+ .txq_agg_enable = iwlagn_txq_agg_enable,
|
|
|
+ .txq_agg_disable = iwlagn_txq_agg_disable,
|
|
|
.txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
|
|
|
.txq_free_tfd = iwl_hw_txq_free_tfd,
|
|
|
.txq_init = iwl_hw_tx_queue_init,
|
|
|
- .rx_handler_setup = iwl5000_rx_handler_setup,
|
|
|
- .setup_deferred_work = iwl5000_setup_deferred_work,
|
|
|
- .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
|
|
|
+ .rx_handler_setup = iwlagn_rx_handler_setup,
|
|
|
+ .setup_deferred_work = iwlagn_setup_deferred_work,
|
|
|
+ .is_valid_rtc_data_addr = iwlagn_hw_valid_rtc_data_addr,
|
|
|
.dump_nic_event_log = iwl_dump_nic_event_log,
|
|
|
.dump_nic_error_log = iwl_dump_nic_error_log,
|
|
|
.dump_csr = iwl_dump_csr,
|
|
|
- .load_ucode = iwl5000_load_ucode,
|
|
|
- .init_alive_start = iwl5000_init_alive_start,
|
|
|
- .alive_notify = iwl5000_alive_notify,
|
|
|
- .send_tx_power = iwl5000_send_tx_power,
|
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|
+ .load_ucode = iwlagn_load_ucode,
|
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|
+ .init_alive_start = iwlagn_init_alive_start,
|
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|
+ .alive_notify = iwlagn_alive_notify,
|
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|
+ .send_tx_power = iwlagn_send_tx_power,
|
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|
.update_chain_flags = iwl_update_chain_flags,
|
|
|
.set_channel_switch = iwl5000_hw_channel_switch,
|
|
|
.apm_ops = {
|
|
|
@@ -1534,19 +355,19 @@ static struct iwl_lib_ops iwl5150_lib = {
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|
},
|
|
|
.eeprom_ops = {
|
|
|
.regulatory_bands = {
|
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- EEPROM_5000_REG_BAND_1_CHANNELS,
|
|
|
- EEPROM_5000_REG_BAND_2_CHANNELS,
|
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|
- EEPROM_5000_REG_BAND_3_CHANNELS,
|
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- EEPROM_5000_REG_BAND_4_CHANNELS,
|
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|
- EEPROM_5000_REG_BAND_5_CHANNELS,
|
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- EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
|
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- EEPROM_5000_REG_BAND_52_HT40_CHANNELS
|
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|
+ EEPROM_REG_BAND_1_CHANNELS,
|
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|
+ EEPROM_REG_BAND_2_CHANNELS,
|
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+ EEPROM_REG_BAND_3_CHANNELS,
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+ EEPROM_REG_BAND_4_CHANNELS,
|
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+ EEPROM_REG_BAND_5_CHANNELS,
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+ EEPROM_REG_BAND_24_HT40_CHANNELS,
|
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+ EEPROM_REG_BAND_52_HT40_CHANNELS
|
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},
|
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|
.verify_signature = iwlcore_eeprom_verify_signature,
|
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|
.acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
|
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|
.release_semaphore = iwlcore_eeprom_release_semaphore,
|
|
|
- .calib_version = iwl5000_eeprom_calib_version,
|
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|
- .query_addr = iwl5000_eeprom_query_addr,
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|
+ .calib_version = iwlagn_eeprom_calib_version,
|
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|
+ .query_addr = iwlagn_eeprom_query_addr,
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|
},
|
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|
.post_associate = iwl_post_associate,
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|
.isr = iwl_isr_ict,
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|
@@ -1562,28 +383,21 @@ static struct iwl_lib_ops iwl5150_lib = {
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|
};
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|
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|
static const struct iwl_ops iwl5000_ops = {
|
|
|
- .ucode = &iwl5000_ucode,
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|
|
+ .ucode = &iwlagn_ucode,
|
|
|
.lib = &iwl5000_lib,
|
|
|
- .hcmd = &iwl5000_hcmd,
|
|
|
- .utils = &iwl5000_hcmd_utils,
|
|
|
+ .hcmd = &iwlagn_hcmd,
|
|
|
+ .utils = &iwlagn_hcmd_utils,
|
|
|
.led = &iwlagn_led_ops,
|
|
|
};
|
|
|
|
|
|
static const struct iwl_ops iwl5150_ops = {
|
|
|
- .ucode = &iwl5000_ucode,
|
|
|
+ .ucode = &iwlagn_ucode,
|
|
|
.lib = &iwl5150_lib,
|
|
|
- .hcmd = &iwl5000_hcmd,
|
|
|
- .utils = &iwl5000_hcmd_utils,
|
|
|
+ .hcmd = &iwlagn_hcmd,
|
|
|
+ .utils = &iwlagn_hcmd_utils,
|
|
|
.led = &iwlagn_led_ops,
|
|
|
};
|
|
|
|
|
|
-struct iwl_mod_params iwl50_mod_params = {
|
|
|
- .amsdu_size_8K = 1,
|
|
|
- .restart_fw = 1,
|
|
|
- /* the rest are 0 by default */
|
|
|
-};
|
|
|
-
|
|
|
-
|
|
|
struct iwl_cfg iwl5300_agn_cfg = {
|
|
|
.name = "Intel(R) Ultimate N WiFi Link 5300 AGN",
|
|
|
.fw_name_pre = IWL5000_FW_PRE,
|
|
|
@@ -1591,12 +405,12 @@ struct iwl_cfg iwl5300_agn_cfg = {
|
|
|
.ucode_api_min = IWL5000_UCODE_API_MIN,
|
|
|
.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
|
|
|
.ops = &iwl5000_ops,
|
|
|
- .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
|
|
|
+ .eeprom_size = IWLAGN_EEPROM_IMG_SIZE,
|
|
|
.eeprom_ver = EEPROM_5000_EEPROM_VERSION,
|
|
|
.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
|
|
|
- .num_of_queues = IWL50_NUM_QUEUES,
|
|
|
- .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
|
|
|
- .mod_params = &iwl50_mod_params,
|
|
|
+ .num_of_queues = IWLAGN_NUM_QUEUES,
|
|
|
+ .num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
|
|
|
+ .mod_params = &iwlagn_mod_params,
|
|
|
.valid_tx_ant = ANT_ABC,
|
|
|
.valid_rx_ant = ANT_ABC,
|
|
|
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
|
|
|
@@ -1609,6 +423,7 @@ struct iwl_cfg iwl5300_agn_cfg = {
|
|
|
.plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
|
|
|
.chain_noise_scale = 1000,
|
|
|
.monitor_recover_period = IWL_MONITORING_PERIOD,
|
|
|
+ .max_event_log_size = 512,
|
|
|
};
|
|
|
|
|
|
struct iwl_cfg iwl5100_bgn_cfg = {
|
|
|
@@ -1618,12 +433,12 @@ struct iwl_cfg iwl5100_bgn_cfg = {
|
|
|
.ucode_api_min = IWL5000_UCODE_API_MIN,
|
|
|
.sku = IWL_SKU_G|IWL_SKU_N,
|
|
|
.ops = &iwl5000_ops,
|
|
|
- .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
|
|
|
+ .eeprom_size = IWLAGN_EEPROM_IMG_SIZE,
|
|
|
.eeprom_ver = EEPROM_5000_EEPROM_VERSION,
|
|
|
.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
|
|
|
- .num_of_queues = IWL50_NUM_QUEUES,
|
|
|
- .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
|
|
|
- .mod_params = &iwl50_mod_params,
|
|
|
+ .num_of_queues = IWLAGN_NUM_QUEUES,
|
|
|
+ .num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
|
|
|
+ .mod_params = &iwlagn_mod_params,
|
|
|
.valid_tx_ant = ANT_B,
|
|
|
.valid_rx_ant = ANT_AB,
|
|
|
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
|
|
|
@@ -1636,6 +451,7 @@ struct iwl_cfg iwl5100_bgn_cfg = {
|
|
|
.plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
|
|
|
.chain_noise_scale = 1000,
|
|
|
.monitor_recover_period = IWL_MONITORING_PERIOD,
|
|
|
+ .max_event_log_size = 512,
|
|
|
};
|
|
|
|
|
|
struct iwl_cfg iwl5100_abg_cfg = {
|
|
|
@@ -1645,12 +461,12 @@ struct iwl_cfg iwl5100_abg_cfg = {
|
|
|
.ucode_api_min = IWL5000_UCODE_API_MIN,
|
|
|
.sku = IWL_SKU_A|IWL_SKU_G,
|
|
|
.ops = &iwl5000_ops,
|
|
|
- .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
|
|
|
+ .eeprom_size = IWLAGN_EEPROM_IMG_SIZE,
|
|
|
.eeprom_ver = EEPROM_5000_EEPROM_VERSION,
|
|
|
.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
|
|
|
- .num_of_queues = IWL50_NUM_QUEUES,
|
|
|
- .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
|
|
|
- .mod_params = &iwl50_mod_params,
|
|
|
+ .num_of_queues = IWLAGN_NUM_QUEUES,
|
|
|
+ .num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
|
|
|
+ .mod_params = &iwlagn_mod_params,
|
|
|
.valid_tx_ant = ANT_B,
|
|
|
.valid_rx_ant = ANT_AB,
|
|
|
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
|
|
|
@@ -1661,6 +477,7 @@ struct iwl_cfg iwl5100_abg_cfg = {
|
|
|
.plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
|
|
|
.chain_noise_scale = 1000,
|
|
|
.monitor_recover_period = IWL_MONITORING_PERIOD,
|
|
|
+ .max_event_log_size = 512,
|
|
|
};
|
|
|
|
|
|
struct iwl_cfg iwl5100_agn_cfg = {
|
|
|
@@ -1670,12 +487,12 @@ struct iwl_cfg iwl5100_agn_cfg = {
|
|
|
.ucode_api_min = IWL5000_UCODE_API_MIN,
|
|
|
.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
|
|
|
.ops = &iwl5000_ops,
|
|
|
- .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
|
|
|
+ .eeprom_size = IWLAGN_EEPROM_IMG_SIZE,
|
|
|
.eeprom_ver = EEPROM_5000_EEPROM_VERSION,
|
|
|
.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
|
|
|
- .num_of_queues = IWL50_NUM_QUEUES,
|
|
|
- .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
|
|
|
- .mod_params = &iwl50_mod_params,
|
|
|
+ .num_of_queues = IWLAGN_NUM_QUEUES,
|
|
|
+ .num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
|
|
|
+ .mod_params = &iwlagn_mod_params,
|
|
|
.valid_tx_ant = ANT_B,
|
|
|
.valid_rx_ant = ANT_AB,
|
|
|
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
|
|
|
@@ -1688,6 +505,7 @@ struct iwl_cfg iwl5100_agn_cfg = {
|
|
|
.plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
|
|
|
.chain_noise_scale = 1000,
|
|
|
.monitor_recover_period = IWL_MONITORING_PERIOD,
|
|
|
+ .max_event_log_size = 512,
|
|
|
};
|
|
|
|
|
|
struct iwl_cfg iwl5350_agn_cfg = {
|
|
|
@@ -1697,12 +515,12 @@ struct iwl_cfg iwl5350_agn_cfg = {
|
|
|
.ucode_api_min = IWL5000_UCODE_API_MIN,
|
|
|
.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
|
|
|
.ops = &iwl5000_ops,
|
|
|
- .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
|
|
|
+ .eeprom_size = IWLAGN_EEPROM_IMG_SIZE,
|
|
|
.eeprom_ver = EEPROM_5050_EEPROM_VERSION,
|
|
|
.eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
|
|
|
- .num_of_queues = IWL50_NUM_QUEUES,
|
|
|
- .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
|
|
|
- .mod_params = &iwl50_mod_params,
|
|
|
+ .num_of_queues = IWLAGN_NUM_QUEUES,
|
|
|
+ .num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
|
|
|
+ .mod_params = &iwlagn_mod_params,
|
|
|
.valid_tx_ant = ANT_ABC,
|
|
|
.valid_rx_ant = ANT_ABC,
|
|
|
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
|
|
|
@@ -1715,6 +533,7 @@ struct iwl_cfg iwl5350_agn_cfg = {
|
|
|
.plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
|
|
|
.chain_noise_scale = 1000,
|
|
|
.monitor_recover_period = IWL_MONITORING_PERIOD,
|
|
|
+ .max_event_log_size = 512,
|
|
|
};
|
|
|
|
|
|
struct iwl_cfg iwl5150_agn_cfg = {
|
|
|
@@ -1724,12 +543,12 @@ struct iwl_cfg iwl5150_agn_cfg = {
|
|
|
.ucode_api_min = IWL5150_UCODE_API_MIN,
|
|
|
.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
|
|
|
.ops = &iwl5150_ops,
|
|
|
- .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
|
|
|
+ .eeprom_size = IWLAGN_EEPROM_IMG_SIZE,
|
|
|
.eeprom_ver = EEPROM_5050_EEPROM_VERSION,
|
|
|
.eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
|
|
|
- .num_of_queues = IWL50_NUM_QUEUES,
|
|
|
- .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
|
|
|
- .mod_params = &iwl50_mod_params,
|
|
|
+ .num_of_queues = IWLAGN_NUM_QUEUES,
|
|
|
+ .num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
|
|
|
+ .mod_params = &iwlagn_mod_params,
|
|
|
.valid_tx_ant = ANT_A,
|
|
|
.valid_rx_ant = ANT_AB,
|
|
|
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
|
|
|
@@ -1742,6 +561,7 @@ struct iwl_cfg iwl5150_agn_cfg = {
|
|
|
.plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
|
|
|
.chain_noise_scale = 1000,
|
|
|
.monitor_recover_period = IWL_MONITORING_PERIOD,
|
|
|
+ .max_event_log_size = 512,
|
|
|
};
|
|
|
|
|
|
struct iwl_cfg iwl5150_abg_cfg = {
|
|
|
@@ -1751,12 +571,12 @@ struct iwl_cfg iwl5150_abg_cfg = {
|
|
|
.ucode_api_min = IWL5150_UCODE_API_MIN,
|
|
|
.sku = IWL_SKU_A|IWL_SKU_G,
|
|
|
.ops = &iwl5150_ops,
|
|
|
- .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
|
|
|
+ .eeprom_size = IWLAGN_EEPROM_IMG_SIZE,
|
|
|
.eeprom_ver = EEPROM_5050_EEPROM_VERSION,
|
|
|
.eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
|
|
|
- .num_of_queues = IWL50_NUM_QUEUES,
|
|
|
- .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
|
|
|
- .mod_params = &iwl50_mod_params,
|
|
|
+ .num_of_queues = IWLAGN_NUM_QUEUES,
|
|
|
+ .num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
|
|
|
+ .mod_params = &iwlagn_mod_params,
|
|
|
.valid_tx_ant = ANT_A,
|
|
|
.valid_rx_ant = ANT_AB,
|
|
|
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
|
|
|
@@ -1767,20 +587,8 @@ struct iwl_cfg iwl5150_abg_cfg = {
|
|
|
.plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
|
|
|
.chain_noise_scale = 1000,
|
|
|
.monitor_recover_period = IWL_MONITORING_PERIOD,
|
|
|
+ .max_event_log_size = 512,
|
|
|
};
|
|
|
|
|
|
MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
|
|
|
MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
|
|
|
-
|
|
|
-module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO);
|
|
|
-MODULE_PARM_DESC(swcrypto50,
|
|
|
- "using software crypto engine (default 0 [hardware])\n");
|
|
|
-module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO);
|
|
|
-MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
|
|
|
-module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO);
|
|
|
-MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
|
|
|
-module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K,
|
|
|
- int, S_IRUGO);
|
|
|
-MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
|
|
|
-module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO);
|
|
|
-MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
|