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+/*
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+ * cec-pin-priv.h - internal cec-pin header
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+ *
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+ * Copyright 2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
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+ *
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+ * This program is free software; you may redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; version 2 of the License.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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+ * SOFTWARE.
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+ */
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+
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+#ifndef LINUX_CEC_PIN_PRIV_H
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+#define LINUX_CEC_PIN_PRIV_H
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+
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+#include <linux/types.h>
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+#include <linux/atomic.h>
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+#include <media/cec-pin.h>
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+
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+enum cec_pin_state {
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+ /* CEC is off */
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+ CEC_ST_OFF,
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+ /* CEC is idle, waiting for Rx or Tx */
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+ CEC_ST_IDLE,
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+
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+ /* Tx states */
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+
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+ /* Pending Tx, waiting for Signal Free Time to expire */
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+ CEC_ST_TX_WAIT,
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+ /* Low-drive was detected, wait for bus to go high */
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+ CEC_ST_TX_WAIT_FOR_HIGH,
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+ /* Drive CEC low for the start bit */
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+ CEC_ST_TX_START_BIT_LOW,
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+ /* Drive CEC high for the start bit */
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+ CEC_ST_TX_START_BIT_HIGH,
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+ /* Drive CEC low for the 0 bit */
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+ CEC_ST_TX_DATA_BIT_0_LOW,
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+ /* Drive CEC high for the 0 bit */
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+ CEC_ST_TX_DATA_BIT_0_HIGH,
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+ /* Drive CEC low for the 1 bit */
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+ CEC_ST_TX_DATA_BIT_1_LOW,
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+ /* Drive CEC high for the 1 bit */
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+ CEC_ST_TX_DATA_BIT_1_HIGH,
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+ /*
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+ * Wait for start of sample time to check for Ack bit or first
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+ * four initiator bits to check for Arbitration Lost.
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+ */
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+ CEC_ST_TX_DATA_BIT_1_HIGH_PRE_SAMPLE,
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+ /* Wait for end of bit period after sampling */
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+ CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE,
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+
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+ /* Rx states */
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+
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+ /* Start bit low detected */
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+ CEC_ST_RX_START_BIT_LOW,
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+ /* Start bit high detected */
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+ CEC_ST_RX_START_BIT_HIGH,
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+ /* Wait for bit sample time */
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+ CEC_ST_RX_DATA_SAMPLE,
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+ /* Wait for earliest end of bit period after sampling */
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+ CEC_ST_RX_DATA_POST_SAMPLE,
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+ /* Wait for CEC to go high (i.e. end of bit period */
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+ CEC_ST_RX_DATA_HIGH,
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+ /* Drive CEC low to send 0 Ack bit */
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+ CEC_ST_RX_ACK_LOW,
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+ /* End of 0 Ack time, wait for earliest end of bit period */
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+ CEC_ST_RX_ACK_LOW_POST,
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+ /* Wait for CEC to go high (i.e. end of bit period */
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+ CEC_ST_RX_ACK_HIGH_POST,
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+ /* Wait for earliest end of bit period and end of message */
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+ CEC_ST_RX_ACK_FINISH,
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+
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+ /* Start low drive */
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+ CEC_ST_LOW_DRIVE,
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+ /* Monitor pin using interrupts */
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+ CEC_ST_RX_IRQ,
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+
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+ /* Total number of pin states */
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+ CEC_PIN_STATES
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+};
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+
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+#define CEC_NUM_PIN_EVENTS 128
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+
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+#define CEC_PIN_IRQ_UNCHANGED 0
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+#define CEC_PIN_IRQ_DISABLE 1
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+#define CEC_PIN_IRQ_ENABLE 2
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+
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+struct cec_pin {
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+ struct cec_adapter *adap;
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+ const struct cec_pin_ops *ops;
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+ struct task_struct *kthread;
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+ wait_queue_head_t kthread_waitq;
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+ struct hrtimer timer;
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+ ktime_t ts;
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+ unsigned int wait_usecs;
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+ u16 la_mask;
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+ bool enabled;
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+ bool monitor_all;
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+ bool rx_eom;
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+ bool enable_irq_failed;
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+ enum cec_pin_state state;
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+ struct cec_msg tx_msg;
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+ u32 tx_bit;
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+ bool tx_nacked;
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+ u32 tx_signal_free_time;
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+ struct cec_msg rx_msg;
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+ u32 rx_bit;
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+
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+ struct cec_msg work_rx_msg;
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+ u8 work_tx_status;
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+ ktime_t work_tx_ts;
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+ atomic_t work_irq_change;
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+ atomic_t work_pin_events;
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+ unsigned int work_pin_events_wr;
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+ unsigned int work_pin_events_rd;
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+ ktime_t work_pin_ts[CEC_NUM_PIN_EVENTS];
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+ bool work_pin_is_high[CEC_NUM_PIN_EVENTS];
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+ ktime_t timer_ts;
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+ u32 timer_cnt;
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+ u32 timer_100ms_overruns;
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+ u32 timer_300ms_overruns;
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+ u32 timer_max_overrun;
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+ u32 timer_sum_overrun;
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+};
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+
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+#endif
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