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@@ -4507,6 +4507,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
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struct intel_atomic_state *state =
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to_intel_atomic_state(cstate->base.state);
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bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
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+ uint32_t min_disp_buf_needed;
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if (latency == 0 ||
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!intel_wm_plane_visible(cstate, intel_pstate)) {
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@@ -4565,7 +4566,31 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
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}
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}
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- if (res_blocks >= ddb_allocation || res_lines > 31) {
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+ if (INTEL_GEN(dev_priv) >= 11) {
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+ if (wp->y_tiled) {
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+ uint32_t extra_lines;
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+ uint_fixed_16_16_t fp_min_disp_buf_needed;
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+
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+ if (res_lines % wp->y_min_scanlines == 0)
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+ extra_lines = wp->y_min_scanlines;
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+ else
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+ extra_lines = wp->y_min_scanlines * 2 -
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+ res_lines % wp->y_min_scanlines;
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+
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+ fp_min_disp_buf_needed = mul_u32_fixed16(res_lines +
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+ extra_lines,
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+ wp->plane_blocks_per_line);
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+ min_disp_buf_needed = fixed16_to_u32_round_up(
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+ fp_min_disp_buf_needed);
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+ } else {
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+ min_disp_buf_needed = DIV_ROUND_UP(res_blocks * 11, 10);
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+ }
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+ } else {
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+ min_disp_buf_needed = res_blocks;
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+ }
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+
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+ if (res_blocks >= ddb_allocation || res_lines > 31 ||
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+ min_disp_buf_needed >= ddb_allocation) {
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*enabled = false;
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/*
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