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@@ -58,6 +58,7 @@
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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clock-frequency = <1800000000>;
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+ cci-control-port = <&cci_control1>;
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};
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cpu1: cpu@1 {
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@@ -65,6 +66,7 @@
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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clock-frequency = <1800000000>;
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+ cci-control-port = <&cci_control1>;
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};
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cpu2: cpu@2 {
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@@ -72,6 +74,7 @@
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compatible = "arm,cortex-a15";
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reg = <0x2>;
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clock-frequency = <1800000000>;
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+ cci-control-port = <&cci_control1>;
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};
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cpu3: cpu@3 {
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@@ -79,6 +82,7 @@
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compatible = "arm,cortex-a15";
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reg = <0x3>;
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clock-frequency = <1800000000>;
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+ cci-control-port = <&cci_control1>;
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};
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cpu4: cpu@100 {
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@@ -86,6 +90,7 @@
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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clock-frequency = <1000000000>;
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+ cci-control-port = <&cci_control0>;
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};
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cpu5: cpu@101 {
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@@ -93,6 +98,7 @@
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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clock-frequency = <1000000000>;
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+ cci-control-port = <&cci_control0>;
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};
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cpu6: cpu@102 {
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@@ -100,6 +106,7 @@
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compatible = "arm,cortex-a7";
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reg = <0x102>;
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clock-frequency = <1000000000>;
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+ cci-control-port = <&cci_control0>;
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};
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cpu7: cpu@103 {
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@@ -107,6 +114,26 @@
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compatible = "arm,cortex-a7";
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reg = <0x103>;
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clock-frequency = <1000000000>;
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+ cci-control-port = <&cci_control0>;
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+ };
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+ };
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+
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+ cci@10d20000 {
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+ compatible = "arm,cci-400";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ reg = <0x10d20000 0x1000>;
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+ ranges = <0x0 0x10d20000 0x6000>;
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+
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+ cci_control0: slave-if@4000 {
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+ compatible = "arm,cci-400-ctrl-if";
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+ interface-type = "ace";
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+ reg = <0x4000 0x1000>;
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+ };
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+ cci_control1: slave-if@5000 {
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+ compatible = "arm,cci-400-ctrl-if";
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+ interface-type = "ace";
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+ reg = <0x5000 0x1000>;
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};
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};
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