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@@ -682,33 +682,3 @@ int cn23xx_setup_octeon_vf_device(struct octeon_device *oct)
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return 0;
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}
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-
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-void cn23xx_dump_vf_iq_regs(struct octeon_device *oct)
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-{
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- u32 regval, q_no;
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-
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- dev_dbg(&oct->pci_dev->dev, "SLI_IQ_DOORBELL_0 [0x%x]: 0x%016llx\n",
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- CN23XX_VF_SLI_IQ_DOORBELL(0),
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- CVM_CAST64(octeon_read_csr64(
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- oct, CN23XX_VF_SLI_IQ_DOORBELL(0))));
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-
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- dev_dbg(&oct->pci_dev->dev, "SLI_IQ_BASEADDR_0 [0x%x]: 0x%016llx\n",
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- CN23XX_VF_SLI_IQ_BASE_ADDR64(0),
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- CVM_CAST64(octeon_read_csr64(
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- oct, CN23XX_VF_SLI_IQ_BASE_ADDR64(0))));
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-
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- dev_dbg(&oct->pci_dev->dev, "SLI_IQ_FIFO_RSIZE_0 [0x%x]: 0x%016llx\n",
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- CN23XX_VF_SLI_IQ_SIZE(0),
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- CVM_CAST64(octeon_read_csr64(oct, CN23XX_VF_SLI_IQ_SIZE(0))));
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-
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- for (q_no = 0; q_no < oct->sriov_info.rings_per_vf; q_no++) {
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- dev_dbg(&oct->pci_dev->dev, "SLI_PKT[%d]_INPUT_CTL [0x%x]: 0x%016llx\n",
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- q_no, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no),
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- CVM_CAST64(octeon_read_csr64(
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- oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no))));
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- }
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-
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- pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, ®val);
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- dev_dbg(&oct->pci_dev->dev, "Config DevCtl [0x%x]: 0x%08x\n",
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- CN23XX_CONFIG_PCIE_DEVCTL, regval);
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-}
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