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@@ -1028,7 +1028,7 @@ static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result)
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((state->m_hi_cfg_ctrl) &
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((state->m_hi_cfg_ctrl) &
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SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
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SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
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SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
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SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
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- if (powerdown_cmd == false) {
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+ if (!powerdown_cmd) {
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/* Wait until command rdy */
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/* Wait until command rdy */
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u32 retry_count = 0;
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u32 retry_count = 0;
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u16 wait_cmd;
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u16 wait_cmd;
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@@ -1129,7 +1129,7 @@ static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)
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if (status < 0)
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if (status < 0)
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goto error;
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goto error;
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- if (mpeg_enable == false) {
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+ if (!mpeg_enable) {
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/* Set MPEG TS pads to inputmode */
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/* Set MPEG TS pads to inputmode */
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status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
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status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
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if (status < 0)
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if (status < 0)
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@@ -1190,7 +1190,7 @@ static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)
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if (status < 0)
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if (status < 0)
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goto error;
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goto error;
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- if (state->m_enable_parallel == true) {
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+ if (state->m_enable_parallel) {
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/* parallel -> enable MD1 to MD7 */
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/* parallel -> enable MD1 to MD7 */
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status = write16(state, SIO_PDR_MD1_CFG__A,
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status = write16(state, SIO_PDR_MD1_CFG__A,
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sio_pdr_mdx_cfg);
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sio_pdr_mdx_cfg);
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@@ -1392,7 +1392,7 @@ static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable)
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dprintk(1, "\n");
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dprintk(1, "\n");
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- if (enable == false) {
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+ if (!enable) {
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desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
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desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
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desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
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desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
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}
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}
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@@ -2012,7 +2012,7 @@ static int mpegts_dto_setup(struct drxk_state *state,
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goto error;
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goto error;
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fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
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fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
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fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
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fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
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- if (state->m_insert_rs_byte == true) {
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+ if (state->m_insert_rs_byte) {
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/* enable parity symbol forward */
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/* enable parity symbol forward */
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fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
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fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
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/* MVAL disable during parity bytes */
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/* MVAL disable during parity bytes */
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@@ -2023,7 +2023,7 @@ static int mpegts_dto_setup(struct drxk_state *state,
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/* Check serial or parallel output */
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/* Check serial or parallel output */
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fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
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fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
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- if (state->m_enable_parallel == false) {
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+ if (!state->m_enable_parallel) {
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/* MPEG data output is serial -> set ipr_mode[0] */
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/* MPEG data output is serial -> set ipr_mode[0] */
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fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
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fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
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}
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}
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@@ -2136,19 +2136,19 @@ static int mpegts_configure_polarity(struct drxk_state *state)
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/* Control selective inversion of output bits */
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/* Control selective inversion of output bits */
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fec_oc_reg_ipr_invert &= (~(invert_data_mask));
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fec_oc_reg_ipr_invert &= (~(invert_data_mask));
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- if (state->m_invert_data == true)
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+ if (state->m_invert_data)
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fec_oc_reg_ipr_invert |= invert_data_mask;
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fec_oc_reg_ipr_invert |= invert_data_mask;
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fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
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fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
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- if (state->m_invert_err == true)
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+ if (state->m_invert_err)
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fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
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fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
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fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
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fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
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- if (state->m_invert_str == true)
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+ if (state->m_invert_str)
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fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
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fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
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fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
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fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
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- if (state->m_invert_val == true)
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+ if (state->m_invert_val)
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fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
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fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
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fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
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fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
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- if (state->m_invert_clk == true)
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+ if (state->m_invert_clk)
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fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
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fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
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return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert);
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return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert);
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@@ -3352,7 +3352,7 @@ static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled)
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int status;
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int status;
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dprintk(1, "\n");
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dprintk(1, "\n");
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- if (*enabled == true)
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+ if (*enabled)
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status = write16(state, IQM_CF_BYPASSDET__A, 0);
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status = write16(state, IQM_CF_BYPASSDET__A, 0);
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else
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else
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status = write16(state, IQM_CF_BYPASSDET__A, 1);
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status = write16(state, IQM_CF_BYPASSDET__A, 1);
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@@ -3368,7 +3368,7 @@ static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled)
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int status;
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int status;
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dprintk(1, "\n");
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dprintk(1, "\n");
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- if (*enabled == true) {
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+ if (*enabled) {
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/* write mask to 1 */
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/* write mask to 1 */
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status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
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status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
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DEFAULT_FR_THRES_8K);
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DEFAULT_FR_THRES_8K);
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@@ -6794,11 +6794,11 @@ struct dvb_frontend *drxk_attach(const struct drxk_config *config,
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state->enable_merr_cfg = config->enable_merr_cfg;
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state->enable_merr_cfg = config->enable_merr_cfg;
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if (config->dynamic_clk) {
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if (config->dynamic_clk) {
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- state->m_dvbt_static_clk = 0;
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- state->m_dvbc_static_clk = 0;
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+ state->m_dvbt_static_clk = false;
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+ state->m_dvbc_static_clk = false;
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} else {
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} else {
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- state->m_dvbt_static_clk = 1;
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- state->m_dvbc_static_clk = 1;
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+ state->m_dvbt_static_clk = true;
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+ state->m_dvbc_static_clk = true;
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}
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}
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