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drm/amd/display: set HBR3 and TPS4 capable flags

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Zeyu Fan <Zeyu.Fan@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hersen Wu 8 年之前
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5a7a1eebc6
共有 1 個文件被更改,包括 10 次插入0 次删除
  1. 10 0
      drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

+ 10 - 0
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

@@ -1068,9 +1068,19 @@ bool dce110_link_encoder_construct(
 			&bp_cap_info))
 		enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
 				bp_cap_info.DP_HBR2_CAP;
+		enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
+				bp_cap_info.DP_HBR3_EN;
+
 	}
+
+	/* TODO: check PPLIB maxPhyClockInKHz <= 540000, if yes,
+	 * IS_HBR3_CAPABLE = 0.
+	 */
+
 	/* test pattern 3 support */
 	enc110->base.features.flags.bits.IS_TPS3_CAPABLE = true;
+	/* test pattern 4 support */
+	enc110->base.features.flags.bits.IS_TPS4_CAPABLE = true;
 
 	enc110->base.features.flags.bits.IS_Y_ONLY_CAPABLE = false;
 	/*