|
@@ -231,7 +231,7 @@
|
|
|
#define CLKID_AHB_DATA_BUS 60
|
|
|
#define CLKID_AHB_CTRL_BUS 61
|
|
|
#define CLKID_HDMI_INTR_SYNC 62
|
|
|
-#define CLKID_HDMI_PCLK 63
|
|
|
+/* CLKID_HDMI_PCLK */
|
|
|
/* CLKID_USB1_DDR_BRIDGE */
|
|
|
/* CLKID_USB0_DDR_BRIDGE */
|
|
|
#define CLKID_MMC_PCLK 66
|
|
@@ -245,7 +245,7 @@
|
|
|
#define CLKID_VCLK2_VENCI1 74
|
|
|
#define CLKID_VCLK2_VENCP0 75
|
|
|
#define CLKID_VCLK2_VENCP1 76
|
|
|
-#define CLKID_GCLK_VENCI_INT0 77
|
|
|
+/* CLKID_GCLK_VENCI_INT0 */
|
|
|
#define CLKID_GCLK_VENCI_INT 78
|
|
|
#define CLKID_DAC_CLK 79
|
|
|
#define CLKID_AOCLK_GATE 80
|