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@@ -94,7 +94,10 @@
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#define BCE (1 << 1)
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#define FOUR_BIT (1 << 1)
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#define HSPE (1 << 2)
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+#define IWE (1 << 24)
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#define DDR (1 << 19)
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+#define CLKEXTFREE (1 << 16)
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+#define CTPL (1 << 11)
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#define DW8 (1 << 5)
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#define OD 0x1
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#define STAT_CLEAR 0xFFFFFFFF
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@@ -687,6 +690,9 @@ static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
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capa = VS18;
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}
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+ if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
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+ hctl |= IWE;
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+
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OMAP_HSMMC_WRITE(host->base, HCTL,
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OMAP_HSMMC_READ(host->base, HCTL) | hctl);
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@@ -1684,19 +1690,23 @@ static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
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static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
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{
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struct omap_hsmmc_host *host = mmc_priv(mmc);
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- u32 irq_mask;
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+ u32 irq_mask, con;
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unsigned long flags;
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spin_lock_irqsave(&host->irq_lock, flags);
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+ con = OMAP_HSMMC_READ(host->base, CON);
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irq_mask = OMAP_HSMMC_READ(host->base, ISE);
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if (enable) {
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host->flags |= HSMMC_SDIO_IRQ_ENABLED;
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irq_mask |= CIRQ_EN;
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+ con |= CTPL | CLKEXTFREE;
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} else {
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host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
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irq_mask &= ~CIRQ_EN;
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+ con &= ~(CTPL | CLKEXTFREE);
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}
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+ OMAP_HSMMC_WRITE(host->base, CON, con);
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OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
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/*
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@@ -1746,6 +1756,8 @@ static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
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goto err;
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}
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+ OMAP_HSMMC_WRITE(host->base, HCTL,
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+ OMAP_HSMMC_READ(host->base, HCTL) | IWE);
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return 0;
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err:
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