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@@ -12,7 +12,7 @@
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*/
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*/
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/*
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/*
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- * First half is MMU families
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+ * MMU families
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*/
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*/
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#define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001)
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#define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001)
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#define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002)
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#define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002)
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@@ -21,9 +21,13 @@
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#define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
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#define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
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#define MMU_FTR_TYPE_47x ASM_CONST(0x00000020)
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#define MMU_FTR_TYPE_47x ASM_CONST(0x00000020)
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+/* Radix page table supported and enabled */
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+#define MMU_FTR_TYPE_RADIX ASM_CONST(0x00000040)
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+
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/*
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/*
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- * This is individual features
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+ * Individual features below.
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*/
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*/
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+
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/*
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/*
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* We need to clear top 16bits of va (from the remaining 64 bits )in
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* We need to clear top 16bits of va (from the remaining 64 bits )in
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* tlbie* instructions
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* tlbie* instructions
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@@ -93,11 +97,6 @@
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*/
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*/
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#define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
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#define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
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-/*
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- * Radix page table available
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- */
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-#define MMU_FTR_RADIX ASM_CONST(0x80000000)
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-
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/* MMU feature bit sets for various CPUs */
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/* MMU feature bit sets for various CPUs */
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#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
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#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
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MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
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MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
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@@ -131,7 +130,7 @@ enum {
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MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |
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MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |
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MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |
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MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |
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#ifdef CONFIG_PPC_RADIX_MMU
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#ifdef CONFIG_PPC_RADIX_MMU
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- MMU_FTR_RADIX |
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+ MMU_FTR_TYPE_RADIX |
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#endif
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#endif
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0,
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0,
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};
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};
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