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@@ -4595,17 +4595,17 @@ static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
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* used when we know that the CRTC isn't feeding multiple encoders!
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*/
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static struct intel_encoder *
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-intel_get_crtc_new_encoder(const struct intel_crtc_state *crtc_state)
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+intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
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+ const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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- const struct drm_atomic_state *state = crtc_state->base.state;
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const struct drm_connector_state *connector_state;
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const struct drm_connector *connector;
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struct intel_encoder *encoder = NULL;
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int num_encoders = 0;
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int i;
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- for_each_new_connector_in_state(state, connector, connector_state, i) {
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+ for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
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if (connector_state->crtc != &crtc->base)
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continue;
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@@ -4619,22 +4619,6 @@ intel_get_crtc_new_encoder(const struct intel_crtc_state *crtc_state)
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return encoder;
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}
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-/* Return which DP Port should be selected for Transcoder DP control */
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-static enum port
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-intel_trans_dp_port_sel(struct intel_crtc *crtc)
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-{
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- struct drm_device *dev = crtc->base.dev;
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- struct intel_encoder *encoder;
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-
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- for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
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- if (encoder->type == INTEL_OUTPUT_DP ||
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- encoder->type == INTEL_OUTPUT_EDP)
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- return encoder->port;
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- }
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-
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- return -1;
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-}
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-
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/*
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* Enable PCH resources required for PCH ports:
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* - PCH PLLs
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@@ -4643,7 +4627,8 @@ intel_trans_dp_port_sel(struct intel_crtc *crtc)
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* - DP transcoding bits
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* - transcoder
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*/
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-static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
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+static void ironlake_pch_enable(const struct intel_atomic_state *state,
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+ const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_device *dev = crtc->base.dev;
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@@ -4716,7 +4701,7 @@ static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
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if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
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temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
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- port = intel_trans_dp_port_sel(crtc);
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+ port = intel_get_crtc_new_encoder(state, crtc_state)->port;
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WARN_ON(port < PORT_B || port > PORT_D);
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temp |= TRANS_DP_PORT_SEL(port);
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@@ -4726,7 +4711,8 @@ static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
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ironlake_enable_pch_transcoder(dev_priv, pipe);
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}
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-static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
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+static void lpt_pch_enable(const struct intel_atomic_state *state,
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+ const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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@@ -5529,7 +5515,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
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intel_enable_pipe(pipe_config);
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if (intel_crtc->config->has_pch_encoder)
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- ironlake_pch_enable(pipe_config);
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+ ironlake_pch_enable(old_intel_state, pipe_config);
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assert_vblank_disabled(crtc);
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drm_crtc_vblank_on(crtc);
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@@ -5668,7 +5654,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
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intel_enable_pipe(pipe_config);
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if (intel_crtc->config->has_pch_encoder)
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- lpt_pch_enable(pipe_config);
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+ lpt_pch_enable(old_intel_state, pipe_config);
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if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
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intel_ddi_set_vc_payload_alloc(pipe_config, true);
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@@ -9122,9 +9108,12 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
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static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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{
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+ struct intel_atomic_state *state =
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+ to_intel_atomic_state(crtc_state->base.state);
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+
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if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
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struct intel_encoder *encoder =
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- intel_get_crtc_new_encoder(crtc_state);
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+ intel_get_crtc_new_encoder(state, crtc_state);
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if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
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DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
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