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@@ -83,7 +83,7 @@
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#define MII_88E1121_PHY_MSCR_REG 21
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#define MII_88E1121_PHY_MSCR_REG 21
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#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
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#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
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#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
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#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
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-#define MII_88E1121_PHY_MSCR_DELAY_MASK (~(BIT(5) || BIT(4)))
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+#define MII_88E1121_PHY_MSCR_DELAY_MASK (~(BIT(5) | BIT(4)))
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#define MII_88E1121_MISC_TEST 0x1a
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#define MII_88E1121_MISC_TEST 0x1a
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#define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00
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#define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00
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