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@@ -195,7 +195,6 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
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val = c->plat->dma_read(CCR, c->dma_ch);
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val = c->plat->dma_read(CCR, c->dma_ch);
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val |= CCR_ENABLE;
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val |= CCR_ENABLE;
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- mb();
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c->plat->dma_write(val, CCR, c->dma_ch);
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c->plat->dma_write(val, CCR, c->dma_ch);
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}
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}
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@@ -301,6 +300,13 @@ static void omap_dma_start_desc(struct omap_chan *c)
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c->desc = d = to_omap_dma_desc(&vd->tx);
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c->desc = d = to_omap_dma_desc(&vd->tx);
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c->sgidx = 0;
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c->sgidx = 0;
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+ /*
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+ * This provides the necessary barrier to ensure data held in
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+ * DMA coherent memory is visible to the DMA engine prior to
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+ * the transfer starting.
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+ */
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+ mb();
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+
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c->plat->dma_write(d->ccr, CCR, c->dma_ch);
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c->plat->dma_write(d->ccr, CCR, c->dma_ch);
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if (dma_omap1())
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if (dma_omap1())
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c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch);
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c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch);
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