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@@ -67,7 +67,7 @@
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*/
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*/
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#define HCR_GUEST_MASK (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \
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#define HCR_GUEST_MASK (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \
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HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \
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HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \
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- HCR_SWIO | HCR_TIDCP)
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+ HCR_TWE | HCR_SWIO | HCR_TIDCP)
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#define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF)
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#define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF)
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/* System Control Register (SCTLR) bits */
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/* System Control Register (SCTLR) bits */
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@@ -208,6 +208,8 @@
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#define HSR_EC_DABT (0x24)
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#define HSR_EC_DABT (0x24)
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#define HSR_EC_DABT_HYP (0x25)
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#define HSR_EC_DABT_HYP (0x25)
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+#define HSR_WFI_IS_WFE (1U << 0)
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+
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#define HSR_HVC_IMM_MASK ((1UL << 16) - 1)
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#define HSR_HVC_IMM_MASK ((1UL << 16) - 1)
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#define HSR_DABT_S1PTW (1U << 7)
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#define HSR_DABT_S1PTW (1U << 7)
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