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@@ -41,6 +41,7 @@ struct mlx5e_rq_param {
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struct mlx5e_sq_param {
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u32 sqc[MLX5_ST_SZ_DW(sqc)];
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struct mlx5_wq_param wq;
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+ u16 max_inline;
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};
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struct mlx5e_cq_param {
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@@ -514,6 +515,7 @@ static int mlx5e_create_sq(struct mlx5e_channel *c,
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sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
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sq->uar_map = sq->uar.map;
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sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
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+ sq->max_inline = param->max_inline;
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err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
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if (err)
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@@ -1020,6 +1022,7 @@ static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
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MLX5_SET(wq, wq, pd, priv->pdn);
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param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
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+ param->max_inline = priv->params.tx_max_inline;
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}
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static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
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@@ -1703,6 +1706,15 @@ static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
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return 0;
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}
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+u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
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+{
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+ int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
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+
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+ return bf_buf_size -
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+ sizeof(struct mlx5e_tx_wqe) +
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+ 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
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+}
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+
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static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
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struct net_device *netdev,
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int num_comp_vectors)
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@@ -1721,6 +1733,7 @@ static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
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MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
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priv->params.tx_cq_moderation_pkts =
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MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
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+ priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
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priv->params.min_rx_wqes =
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MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
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priv->params.rx_hash_log_tbl_sz =
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