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@@ -715,7 +715,6 @@ static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
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unsigned long clock = 0;
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unsigned long level;
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unsigned long stable_pstate_sclk;
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- struct PP_Clocks clocks;
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unsigned long percentage;
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cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
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@@ -726,8 +725,9 @@ static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
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else
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cz_hwmgr->sclk_dpm.soft_max_clk = table->entries[table->count - 1].clk;
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- /*PECI_GetMinClockSettings(pHwMgr->pPECI, &clocks);*/
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- clock = clocks.engineClock;
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+ clock = hwmgr->display_config.min_core_set_clock;
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+ if (clock == 0)
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+ printk(KERN_ERR "[ powerplay ] min_core_set_clock not set\n");
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if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
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cz_hwmgr->sclk_dpm.hard_min_clk = clock;
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