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@@ -64,7 +64,6 @@ int mxc_iomux_mode(unsigned int pin_mode)
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return ret;
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}
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-EXPORT_SYMBOL(mxc_iomux_mode);
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/*
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* This function configures the pad value for a IOMUX pin.
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@@ -90,7 +89,6 @@ void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
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spin_unlock(&gpio_mux_lock);
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}
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-EXPORT_SYMBOL(mxc_iomux_set_pad);
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/*
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* allocs a single pin:
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@@ -116,7 +114,6 @@ int mxc_iomux_alloc_pin(unsigned int pin, const char *label)
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return 0;
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}
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-EXPORT_SYMBOL(mxc_iomux_alloc_pin);
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int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
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const char *label)
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@@ -137,7 +134,6 @@ setup_error:
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mxc_iomux_release_multiple_pins(pin_list, i);
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return ret;
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}
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-EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
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void mxc_iomux_release_pin(unsigned int pin)
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{
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@@ -146,7 +142,6 @@ void mxc_iomux_release_pin(unsigned int pin)
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if (pad < (PIN_MAX + 1))
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clear_bit(pad, mxc_pin_alloc_map);
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}
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-EXPORT_SYMBOL(mxc_iomux_release_pin);
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void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
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{
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@@ -158,7 +153,6 @@ void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
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p++;
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}
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}
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-EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
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/*
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* This function enables/disables the general purpose function for a particular
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@@ -178,4 +172,3 @@ void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
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__raw_writel(l, IOMUXGPR);
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spin_unlock(&gpio_mux_lock);
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}
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-EXPORT_SYMBOL(mxc_iomux_set_gpr);
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