|
@@ -1742,6 +1742,7 @@ static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
|
|
static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
|
|
static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
|
|
{
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
+ struct radeon_device *rdev = dev->dev_private;
|
|
struct drm_crtc *test_crtc;
|
|
struct drm_crtc *test_crtc;
|
|
struct radeon_crtc *test_radeon_crtc;
|
|
struct radeon_crtc *test_radeon_crtc;
|
|
|
|
|
|
@@ -1751,6 +1752,10 @@ static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
|
|
test_radeon_crtc = to_radeon_crtc(test_crtc);
|
|
test_radeon_crtc = to_radeon_crtc(test_crtc);
|
|
if (test_radeon_crtc->encoder &&
|
|
if (test_radeon_crtc->encoder &&
|
|
ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
|
|
ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
|
|
|
|
+ /* PPLL2 is exclusive to UNIPHYA on DCE61 */
|
|
|
|
+ if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
|
|
|
|
+ test_radeon_crtc->pll_id == ATOM_PPLL2)
|
|
|
|
+ continue;
|
|
/* for DP use the same PLL for all */
|
|
/* for DP use the same PLL for all */
|
|
if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
|
|
if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
|
|
return test_radeon_crtc->pll_id;
|
|
return test_radeon_crtc->pll_id;
|
|
@@ -1772,6 +1777,7 @@ static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
|
|
{
|
|
{
|
|
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
|
|
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
|
|
struct drm_device *dev = crtc->dev;
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
+ struct radeon_device *rdev = dev->dev_private;
|
|
struct drm_crtc *test_crtc;
|
|
struct drm_crtc *test_crtc;
|
|
struct radeon_crtc *test_radeon_crtc;
|
|
struct radeon_crtc *test_radeon_crtc;
|
|
u32 adjusted_clock, test_adjusted_clock;
|
|
u32 adjusted_clock, test_adjusted_clock;
|
|
@@ -1787,6 +1793,10 @@ static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
|
|
test_radeon_crtc = to_radeon_crtc(test_crtc);
|
|
test_radeon_crtc = to_radeon_crtc(test_crtc);
|
|
if (test_radeon_crtc->encoder &&
|
|
if (test_radeon_crtc->encoder &&
|
|
!ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
|
|
!ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
|
|
|
|
+ /* PPLL2 is exclusive to UNIPHYA on DCE61 */
|
|
|
|
+ if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
|
|
|
|
+ test_radeon_crtc->pll_id == ATOM_PPLL2)
|
|
|
|
+ continue;
|
|
/* check if we are already driving this connector with another crtc */
|
|
/* check if we are already driving this connector with another crtc */
|
|
if (test_radeon_crtc->connector == radeon_crtc->connector) {
|
|
if (test_radeon_crtc->connector == radeon_crtc->connector) {
|
|
/* if we are, return that pll */
|
|
/* if we are, return that pll */
|