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@@ -112,26 +112,29 @@ int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level
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PHM_FUNC_CHECK(hwmgr);
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- if (hwmgr->hwmgr_func->force_dpm_level != NULL) {
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+ if (hwmgr->hwmgr_func->force_dpm_level != NULL)
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ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
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- if (ret)
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- return ret;
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-
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- if (hwmgr->hwmgr_func->set_power_profile_state) {
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- if (hwmgr->current_power_profile == AMD_PP_GFX_PROFILE)
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- ret = hwmgr->hwmgr_func->set_power_profile_state(
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- hwmgr,
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- &hwmgr->gfx_power_profile);
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- else if (hwmgr->current_power_profile == AMD_PP_COMPUTE_PROFILE)
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- ret = hwmgr->hwmgr_func->set_power_profile_state(
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- hwmgr,
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- &hwmgr->compute_power_profile);
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- }
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- }
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return ret;
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}
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+int phm_reset_power_profile_state(struct pp_hwmgr *hwmgr)
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+{
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+ int ret = 0;
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+
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+ if (hwmgr->hwmgr_func->set_power_profile_state) {
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+ if (hwmgr->current_power_profile == AMD_PP_GFX_PROFILE)
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+ ret = hwmgr->hwmgr_func->set_power_profile_state(
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+ hwmgr,
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+ &hwmgr->gfx_power_profile);
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+ else if (hwmgr->current_power_profile == AMD_PP_COMPUTE_PROFILE)
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+ ret = hwmgr->hwmgr_func->set_power_profile_state(
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+ hwmgr,
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+ &hwmgr->compute_power_profile);
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+ }
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+ return ret;
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+}
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+
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int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
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struct pp_power_state *adjusted_ps,
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const struct pp_power_state *current_ps)
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